Texas Instruments
Texas Instruments Incorporated (TI) is a global semiconductor design and manufacturing company that develops analog ICs and embedded processors. By employing the worlds brightest minds, TI creates innovations that shape the future of technology. TI is helping more than 100,000 customers transform the future, today.
| Series | Category | # Parts | Status | Description |
|---|---|---|---|---|
| Development Boards, Kits, Programmers | 4 | 1 | The CDCM6208 is a highly versatile, low jitter low power frequency synthesizer which can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or... Read More | |
| Integrated Circuits (ICs) | 2 | 1 | The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS... Read More | |
| Integrated Circuits (ICs) | 2 | 1 | The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS... Read More | |
| Integrated Circuits (ICs) | 2 | 1 | The CDCM6208V2G is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS... Read More | |
| Integrated Circuits (ICs) | 2 | 1 | The CDCM6208V2G is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS... Read More | |
Texas InstrumentsCDCM7005High performance, low phase noise, low skew clock synchronizer that synchronizes ref clock to VCXO | Clock/Timing | 8 | 1 | The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the... Read More |
Texas InstrumentsCDCM7005-SPRadiation-hardened-assured (RHA) 3.3-V high-performance clock jitter cleaner and synchronizer | Integrated Circuits (ICs) | 1 | 10 | The CDCM7005-SP is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the... Read More |
| Clock/Timing | 1 | 1 | The Direct Rambus clock generator (DRCG) provides the necessary clock signals to support a Direct Rambus memory subsystem. It includes signals to synchronize the Direct Rambus channel clock to an external system or processor clock. It is designed to support Direct Rambus memory on a desktop, workstation, server, and mobile... Read More | |
| Clock/Timing | 1 | 1 | The CDCS501 is a spread spectrum capable, LVCMOS Input Clock Buffer for EMI reduction. The device is designed to counter common EMI problems in modern electronic designs. It accepts a 3.3V LVCMOS signal at the input and spread this signal by a small amount, centered around the input frequency. The... Read More | |
| Integrated Circuits (ICs) | 3 | 1 | The CDCS503 is a spread spectrum capable, LVCMOS Input Clock Buffer with selectable frequency multiplication. It shares major functionality with the CDCS502 but utilizes a LVCMOS input stage instead of the crystal input stage of the CDCS502. Also an Output Enable pin has been added to the CDCS503. The device... Read More | |
| Integrated Circuits (ICs) | 1 | 1 | The CDCS503-Q1 device is a spread spectrum capable, LVCMOS input clock buffer with selectable frequency multiplication. It shares major functionality with the CDCS502 but uses a LVCMOS input stage instead of the crystal input stage of the CDCS502, and the CDCS503-Q1 has an output enable pin. The device accepts a... Read More | |
| Clock/Timing | 1 | 10 | The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication. The CDCS504-Q1 has an output enable pin. The device accepts a 3.3-V LVCMOS signal at the input. The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency... Read More | |
| Clock/Timing | 1 | 10 | The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication. The CDCS504-Q1 has an output enable pin. The device accepts a 3.3-V LVCMOS signal at the input. The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency... Read More | |
Texas InstrumentsCDCU2A8771.8-V phase-lock loop clock driver with high output drive for DDR2 SDRAM applications | Integrated Circuits (ICs) | 4 | 1 | The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to 10 differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the... Read More |
| Integrated Circuits (ICs) | 4 | 1 | The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to ten differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the... Read More | |
| Evaluation and Demonstration Boards and Kits | 3 | 1 | The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1,... Read More | |
| Clock/Timing | 2 | 1 | The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1,... Read More | |
| Clock Buffers, Drivers | 1 | 1 | The CDCV304 is a high-performance, low-skew, general-purpose PCI-X compliant clock buffer. It distributes one input clock signal (CLKIN) to the output clocks (1Y[0:3]). It is specifically designed for use with PCI-X applications. The CDCV304 operates at 3.3 V and 2.5 V and is therefore compliant to the 3.3-V PCI-X specifications.... Read More | |
| Integrated Circuits (ICs) | 8 | 4 | The CDCV855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to four differential pairs of clock outputs (Y[0:3], Y[0:3]\) and one differential pair of feedback clock outputs (FBOUT, FBOUT\). When PWRDWN\ is high, the outputs switch in phase and frequency with... Read More | |
Texas InstrumentsCDCV857A2.5-V SSTL-II phase-lock loop clock driver for double data-rate synchronous DRAM applications | Integrated Circuits (ICs) | 2 | 4 | The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the... Read More |