CDCM6208V1F Series

2:8 ultra-low power, low jitter clock generator, pin mode variant F

Link to Manufacturer Page: https://www.ti.com/

Catalog

2:8 ultra-low power, low jitter clock generator, pin mode variant F

Part	Output	Type	Operating Temperature [Min]	Operating Temperature [Max]	Differential - Input:Output [custom]	Differential - Input:Output [custom]	Supplier Device Package	Divider/Multiplier	Package / Case	PLL	Mounting Type	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Input	Voltage - Supply [Max]	Voltage - Supply [Min]	Frequency - Max [Max]	Number of Circuits
Texas Instruments CDCM6208V1FRGZR	CML, HCSL, LVCMOS, LVDS, LVPECL	Clock Generator	-40 °C	85 °C			48-VQFN (7x7)	Yes/No	48-VFQFN Exposed Pad	Yes with Bypass	Surface Mount	2	8	CML, Crystal, LVCMOS, LVDS, LVPECL	3.465 V	1.71 V	800 MHz
Texas Instruments CDCM6208V1FRGZT	CML, HCSL, LVCMOS, LVDS, LVPECL	Clock Generator	-40 °C	85 °C			48-VQFN (7x7)	Yes/No	48-VFQFN Exposed Pad	Yes with Bypass	Surface Mount	2	8	CML, Crystal, LVCMOS, LVDS, LVPECL	3.465 V	1.71 V	800 MHz	1

Key Features

• Superior Performance with Low Power:Low Noise Synthesizer (265 fs-rms TypicalJitter) or Low Noise Jitter Cleaner (1.6 ps-rmsTypical Jitter)0.5 W Typical Power ConsumptionHigh Channel-to-Channel Isolation andExcellent PSRRDevice Performance Customizable ThroughFlexible 1.8 V, 2.5 V and 3.3 V PowerSupplies, Allowing Mixed Output VoltagesFlexible Frequency Planning:4x Integer Down-divided Differential ClockOutputs Supporting LVPECL-like, CML, orLVDS-like Signaling4x Fractional or Integer Divided DifferentialClock Outputs Supporting HCSL, LVDS-likeSignaling, or Eight CMOS OutputsFractional Output Divider Achieve 0 ppm to < 1ppm Frequency Error and Eliminates need forCrystal Oscillators and Other Clock GeneratorsOutput frequencies up to 800 MHzTwo Differential Inputs, XTAL Support, Ability forSmart SwitchingSPI, I2C™, and Pin ProgrammableProfessional user GUI for Quick DesignTurnaround7 × 7 mm 48-QFN package (RGZ)–40 °C to 85 °C temperature rangeSuperior Performance with Low Power:Low Noise Synthesizer (265 fs-rms TypicalJitter) or Low Noise Jitter Cleaner (1.6 ps-rmsTypical Jitter)0.5 W Typical Power ConsumptionHigh Channel-to-Channel Isolation andExcellent PSRRDevice Performance Customizable ThroughFlexible 1.8 V, 2.5 V and 3.3 V PowerSupplies, Allowing Mixed Output VoltagesFlexible Frequency Planning:4x Integer Down-divided Differential ClockOutputs Supporting LVPECL-like, CML, orLVDS-like Signaling4x Fractional or Integer Divided DifferentialClock Outputs Supporting HCSL, LVDS-likeSignaling, or Eight CMOS OutputsFractional Output Divider Achieve 0 ppm to < 1ppm Frequency Error and Eliminates need forCrystal Oscillators and Other Clock GeneratorsOutput frequencies up to 800 MHzTwo Differential Inputs, XTAL Support, Ability forSmart SwitchingSPI, I2C™, and Pin ProgrammableProfessional user GUI for Quick DesignTurnaround7 × 7 mm 48-QFN package (RGZ)–40 °C to 85 °C temperature range

Description

The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features aninnovativefractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins. Insynthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency. Injitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm × 7 mm QFN package. The CDCM6208V1F is a highly versatile, low jitter, low-power frequency synthesizer that can generate eight low jitter clock outputs, selectable between LVPECL-like high-swing CML, normal-swing CML, LVDS-like low-power CML, HCSL, or LVCMOS, from one of two inputs that can feature a low frequency crystal or CML, LVPECL, LVDS, or LVCMOS signals for a variety of wireless infrastructure baseband, wireline data communication, computing, low power medical imaging and portable test and measurement applications. The CDCM6208V1F also features aninnovativefractional divider architecture for four of its outputs that can generate any frequency with better than 1ppm frequency accuracy. The CDCM6208V1F can be easily configured through I2C or SPI programming interface and in the absence of serial interface, pin mode is also available that can set the device in 1 of 32 distinct pre-programmed configurations using control pins. Insynthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k – 20 MHz) or 20 ps-pp (unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k – 40 MHz) on outputs using fractional dividers depending on the prescaler output frequency. Injitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k – 20 MHz) or 40 ps-pp on output using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The CDCM6208V1F is packaged in a small 48-pin 7 mm × 7 mm QFN package.