CDCM7005 Series

High performance, low phase noise, low skew clock synchronizer that synchronizes ref clock to VCXO

Link to Manufacturer Page: https://www.ti.com/

Catalog

High performance, low phase noise, low skew clock synchronizer that synchronizes ref clock to VCXO

Part	Operating Temperature [Min]	Operating Temperature [Max]	Mounting Type	Supplier Device Package	Number of Circuits	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Input	PLL	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]	Frequency - Max [Max]	Output	Divider/Multiplier	Supplied Contents	Contents	Utilized IC / Part	Type	Function
Texas Instruments CDCM7005RGZRG4	-40 °C	85 °C	Surface Mount	48-VQFN (7x7)	1	3	10	LVCMOS, LVPECL	Yes with Bypass	48-VFQFN Exposed Pad	3.6 V	3 V	1.5 GHz	LVCMOS, LVPECL	Yes/No
Texas Instruments CDCM7005ZVAT	-40 °C	85 °C	Surface Mount	64-BGA (8x8)	1	3	10	LVCMOS, LVPECL	Yes with Bypass	64-LFBGA	3.6 V	3 V	1.5 GHz	LVCMOS, LVPECL	Yes/No
Texas Instruments CDCM7005ZVA	-40 °C	85 °C	Surface Mount	64-BGA (8x8)	1	3	10	LVCMOS, LVPECL	Yes with Bypass	64-LFBGA	3.6 V	3 V	1.5 GHz	LVCMOS, LVPECL	Yes/No
Texas Instruments CDCM7005HFG/EM	-40 °C	85 °C	Surface Mount	52-CFP	1	3	10	LVCMOS, LVPECL	Yes with Bypass	52-CFlatPack	3.6 V	3 V	1.5 GHz	LVCMOS, LVPECL
Texas Instruments CDCM7005BGA-EVM																Board(s)	Board(s)	CDCM7005 BGA Package	Timing	Clock Synchronizer
Texas Instruments CDCM7005QFN-EVM																Board(s)		CDCM7005 QFN Package	Timing	Clock Synchronizer
Texas Instruments CDCM7005EVM-CVAL																Board(s)	Board(s)	CDCM7005-SP	Timing	Clock Synchronizer
Texas Instruments CDCM7005RGZTG4	-40 °C	85 °C	Surface Mount	48-VQFN (7x7)	1	3	10	LVCMOS, LVPECL	Yes with Bypass	48-VFQFN Exposed Pad	3.6 V	3 V	1.5 GHz	LVCMOS, LVPECL	Yes/No

Key Features

• High Performance LVPECL and LVCMOS PLL Clock SynchronizerTwo Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic SelectionAccepts LVCMOS Input Frequencies up to 200 MHzVCXO_IN Clock is Synchronized to One of the Two Reference ClocksVCXO_IN Frequencies Up to 2.2 GHz (LVPECL)Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output IndividuallyEfficient Jitter Cleaning From Low PLL Loop BandwidthLow Phase Noise PLL CoreProgrammable Phase Offset (PRI_REF and SEC_REF to Outputs)Wide Charge Pump Current Range From200 µA to 3 mADedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOsPresets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)OAnalog and Digital PLL Lock IndicationProvides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)Frequency Hold-Over Mode Improves Fail-Safe OperationPower-up Control Forces LVPECL Outputs to 3-State at VCC< 1.5 VSPI Controllable Device Setting3.3-V Power SupplyPackaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)Industrial Temperature Range –40°C to 85°CHigh Performance LVPECL and LVCMOS PLL Clock SynchronizerTwo Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic SelectionAccepts LVCMOS Input Frequencies up to 200 MHzVCXO_IN Clock is Synchronized to One of the Two Reference ClocksVCXO_IN Frequencies Up to 2.2 GHz (LVPECL)Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output IndividuallyEfficient Jitter Cleaning From Low PLL Loop BandwidthLow Phase Noise PLL CoreProgrammable Phase Offset (PRI_REF and SEC_REF to Outputs)Wide Charge Pump Current Range From200 µA to 3 mADedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOsPresets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)OAnalog and Digital PLL Lock IndicationProvides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)Frequency Hold-Over Mode Improves Fail-Safe OperationPower-up Control Forces LVPECL Outputs to 3-State at VCC< 1.5 VSPI Controllable Device Setting3.3-V Power SupplyPackaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)Industrial Temperature Range –40°C to 85°C

Description

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C. The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements. The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew. All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire serial peripheral interface). SPI allows individually control of the device settings. The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.