CDCM7005HFG/EM
ActiveRADIATION-HARDENED-ASSURED (RHA) 3.3-V HIGH-PERFORMANCE CLOCK JITTER CLEANER AND SYNCHRONIZER
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CDCM7005HFG/EM
ActiveRADIATION-HARDENED-ASSURED (RHA) 3.3-V HIGH-PERFORMANCE CLOCK JITTER CLEANER AND SYNCHRONIZER
Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CDCM7005HFG/EM | CDCM7005 Series |
|---|---|---|
| Contents | - | Board(s) |
| Differential - Input:Output [custom] | True | True |
| Differential - Input:Output [custom] | True | True |
| Divider/Multiplier | - | Yes/No |
| Frequency - Max [Max] | 1.5 GHz | 1.5 GHz |
| Function | - | Clock Synchronizer |
| Input | LVPECL, LVCMOS | LVPECL, LVCMOS |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Output | LVCMOS, LVPECL | LVCMOS, LVPECL |
| Package / Case | 52-CFlatPack | 48-VFQFN Exposed Pad, 64-LFBGA, 52-CFlatPack |
| PLL | Yes with Bypass | Yes with Bypass |
| Ratio - Input:Output [custom] | 3 | 3 |
| Ratio - Input:Output [custom] | 10 | 10 |
| Supplied Contents | - | Board(s) |
| Supplier Device Package | 52-CFP | 48-VQFN (7x7), 64-BGA (8x8), 52-CFP |
| Type | - | Timing |
| Utilized IC / Part | - | CDCM7005 BGA Package, CDCM7005 QFN Package, CDCM7005-SP |
| Voltage - Supply [Max] | 3.6 V | 3.6 V |
| Voltage - Supply [Min] | 3 V | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 712.98 | |
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 1053.28 | |
| 100 | $ 953.40 | |||
| 250 | $ 926.16 | |||
| 1000 | $ 908.00 | |||
CDCM7005 Series
High performance, low phase noise, low skew clock synchronizer that synchronizes ref clock to VCXO
| Part | Operating Temperature [Min] | Operating Temperature [Max] | Mounting Type | Supplier Device Package | Number of Circuits | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Input | PLL | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] | Frequency - Max [Max] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Output | Divider/Multiplier | Supplied Contents | Contents | Utilized IC / Part | Type | Function |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCM7005RGZRG4 | -40 °C | 85 °C | Surface Mount | 48-VQFN (7x7) | 1 | 3 | 10 | LVCMOS, LVPECL | Yes with Bypass | 48-VFQFN Exposed Pad | 3.6 V | 3 V | 1.5 GHz | LVCMOS, LVPECL | Yes/No | |||||||
Texas Instruments CDCM7005ZVAT | -40 °C | 85 °C | Surface Mount | 64-BGA (8x8) | 1 | 3 | 10 | LVCMOS, LVPECL | Yes with Bypass | 64-LFBGA | 3.6 V | 3 V | 1.5 GHz | LVCMOS, LVPECL | Yes/No | |||||||
Texas Instruments CDCM7005ZVA | -40 °C | 85 °C | Surface Mount | 64-BGA (8x8) | 1 | 3 | 10 | LVCMOS, LVPECL | Yes with Bypass | 64-LFBGA | 3.6 V | 3 V | 1.5 GHz | LVCMOS, LVPECL | Yes/No | |||||||
Texas Instruments CDCM7005HFG/EM | -40 °C | 85 °C | Surface Mount | 52-CFP | 1 | 3 | 10 | LVCMOS, LVPECL | Yes with Bypass | 52-CFlatPack | 3.6 V | 3 V | 1.5 GHz | LVCMOS, LVPECL | ||||||||
Texas Instruments CDCM7005BGA-EVM | Board(s) | Board(s) | CDCM7005 BGA Package | Timing | Clock Synchronizer | |||||||||||||||||
Texas Instruments CDCM7005QFN-EVM | Board(s) | CDCM7005 QFN Package | Timing | Clock Synchronizer | ||||||||||||||||||
Texas Instruments CDCM7005EVM-CVAL | Board(s) | Board(s) | CDCM7005-SP | Timing | Clock Synchronizer | |||||||||||||||||
Texas Instruments CDCM7005RGZTG4 | -40 °C | 85 °C | Surface Mount | 48-VQFN (7x7) | 1 | 3 | 10 | LVCMOS, LVPECL | Yes with Bypass | 48-VFQFN Exposed Pad | 3.6 V | 3 V | 1.5 GHz | LVCMOS, LVPECL | Yes/No |
Description
General part information
CDCM7005 Series
The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O
VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.
The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.
Documents
Technical documentation and resources