CDCV857A Series
2.5-V SSTL-II phase-lock loop clock driver for double data-rate synchronous DRAM applications
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
2.5-V SSTL-II phase-lock loop clock driver for double data-rate synchronous DRAM applications
| Part | Divider/Multiplier [custom] | Divider/Multiplier [custom] | Supplier Device Package | Package / Case [y] | Package / Case | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] | Number of Circuits | Output | Frequency - Max [Max] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Type | Operating Temperature [Min] | Operating Temperature [Max] | Mounting Type | Input | PLL | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCV857ADGGR | 48-TSSOP | 6.1 mm | 48-TFSOP | 0.24 in | 2.7 V | 2.3 V | 1 | Clock | 180 MHz | PLL Clock Driver | 0 °C | 85 °C | Surface Mount | Clock | Yes with Bypass | 1 | 10 | ||||
Texas Instruments CDCV857ADGG | 48-TSSOP | 6.1 mm | 48-TFSOP | 0.24 in | 2.7 V | 2.3 V | 1 | Clock | 180 MHz | PLL Clock Driver | 0 °C | 85 °C | Surface Mount | Clock | Yes with Bypass | 1 | 10 |
Key Features
• Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM ApplicationsSpread Spectrum Clock CompatibleOperating Frequency: 60 to 180 MHzLow Jitter (cyc–cyc): ±50 psDistributes One Differential Clock Input to Ten Differential OutputsThree-State Outputs When the Input Differential Clocks Are <20 MHzOperates From Dual 2.5-V SuppliesAvailable in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA PackageConsumes < 200-uA Quiescent CurrentExternal Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input ClocksMicroStar Junior is a trademark of Texas Instruments Incorporated.Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM ApplicationsSpread Spectrum Clock CompatibleOperating Frequency: 60 to 180 MHzLow Jitter (cyc–cyc): ±50 psDistributes One Differential Clock Input to Ten Differential OutputsThree-State Outputs When the Input Differential Clocks Are <20 MHzOperates From Dual 2.5-V SuppliesAvailable in a 48-Pin TSSOP Package or 56-Ball MicroStar Junior™ BGA PackageConsumes < 200-uA Quiescent CurrentExternal Feedback PIN (FBIN, FBIN\) Are Used to Synchronize the Outputs to the Input ClocksMicroStar Junior is a trademark of Texas Instruments Incorporated.
Description
AI
The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.
When AVDDis strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C.
The CDCV857A is a high-performance, low-skew, low-jitter zero delay buffer that distributes a differential clock input pair (CLK, CLK\) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]\) and one differential pair of feedback clock output (FBOUT, FBOUT\). The clock outputs are controlled by the clock inputs (CLK, CLK\), the feedback clocks (FBIN, FBIN\), and the analog power input (AVDD). When PWRDWN\ is high, the outputs switch in phase and frequency with CLK. When PWRDWN\ is low, all outputs are disabled to high impedance state (3-state), and the PLL is shut down (low power mode). The device also enters this low power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit will detect the low frequency condition and after applying a >20 MHz input signal this detection circuit turns on the PLL again and enables the outputs.
When AVDDis strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C.