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CDCS504 Series

Clock buffer/clock multiplier

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

Clock buffer/clock multiplier

PartGradeFrequency - Max [Max]Number of CircuitsSupplier Device PackageInputQualificationMounting TypeDifferential - Input:Output [custom]Differential - Input:Output [custom]TypeRatio - Input:Output [custom]Operating Temperature [Min]Operating Temperature [Max]OutputVoltage - Supply [Max]Voltage - Supply [Min]Package / Case
Texas Instruments
CDCS504TPWRQ1
Automotive
108 MHz
1
8-TSSOP
LVCMOS
AEC-Q100
Surface Mount
Multiplier
1:1
-40 °C
105 ░C
LVCMOS
3.6 V
3 V
8-TSSOP (0.173", 4.40mm Width)

Key Features

Qualified for Automotive ApplicationsAEC-Q100 Test Guidance With the Following Results:Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature RangeDevice HBM ESD Classification Level H2Device CDM ESD Classification Level C3BPart of a Family of Easy-to-Use Clock Generator DevicesClock Multiplier With Selectable Output FrequencyFrequency Multiplication Selectable Between x1 or x4 With One External Control PinOutput Disable Through Control PinSingle 3.3-V Device Power SupplyWide Temperature Range: –40°C to 105°CLow Space Consumption 8-Pin TSSOP PackageCreate a Custom Design Using the CDCS504-Q1 With theWEBENCH®Power DesignerQualified for Automotive ApplicationsAEC-Q100 Test Guidance With the Following Results:Device Temperature Grade 2: –40°C to 105°C Ambient Operating Temperature RangeDevice HBM ESD Classification Level H2Device CDM ESD Classification Level C3BPart of a Family of Easy-to-Use Clock Generator DevicesClock Multiplier With Selectable Output FrequencyFrequency Multiplication Selectable Between x1 or x4 With One External Control PinOutput Disable Through Control PinSingle 3.3-V Device Power SupplyWide Temperature Range: –40°C to 105°CLow Space Consumption 8-Pin TSSOP PackageCreate a Custom Design Using the CDCS504-Q1 With theWEBENCH®Power Designer

Description

AI
The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication. The CDCS504-Q1 has an output enable pin. The device accepts a 3.3-V LVCMOS signal at the input. The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four. By this, the device can generate output frequencies between 2 MHz and 108 MHz. A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment. It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package. The CDCS504-Q1 device is a LVCMOS input clock buffer with selectable frequency multiplication. The CDCS504-Q1 has an output enable pin. The device accepts a 3.3-V LVCMOS signal at the input. The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four. By this, the device can generate output frequencies between 2 MHz and 108 MHz. A separate control pin can be used to enable or disable the output. The CDCS504-Q1 device operates in a 3.3-V environment. It is characterized for operation from –40°C to 105°C and is available in an 8-pin TSSOP package.