CDCU877A Series

1.8-V phase-lock loop clock driver for DDR2 SDRAM applications

Link to Manufacturer Page: https://www.ti.com/

Catalog

1.8-V phase-lock loop clock driver for DDR2 SDRAM applications

Part	Input	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Supplier Device Package [y]	Supplier Device Package [x]	Frequency - Max [Max]	Number of Circuits	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Operating Temperature [Max]	Operating Temperature [Min]	Output	Mounting Type	Package / Case
Texas Instruments CDCU877ANMKT	Clock	1.7 V	1.9 V	52-NFBGA	4.5	7	400 MHz	1	1	10	85 °C	-40 °C	Clock	Surface Mount
Texas Instruments CDCU877ARHAR	SSTL-18	1.7 V	1.9 V	40-VQFN (6x6)			400 MHz	1	1	10	85 °C	-40 °C	SSTL-18	Surface Mount	40-VFQFN Exposed Pad
Texas Instruments CDCU877ARHAT	SSTL-18	1.7 V	1.9 V	40-VQFN (6x6)			400 MHz	1	1	10	85 °C	-40 °C	SSTL-18	Surface Mount	40-VFQFN Exposed Pad
Texas Instruments CDCU877ANMKR	Clock	1.7 V	1.9 V	52-NFBGA	4.5	7	400 MHz	1	1	10	85 °C	-40 °C	Clock	Surface Mount

Key Features

• 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) ApplicationsSpread Spectrum Clock CompatibleOperating Frequency: 10 MHz to 400 MHzLow Current Consumption: <135 mALow Jitter (Cycle-Cycle): ±30 psLow Output Skew: 35 psLow Period Jitter: ±20 psLow Dynamic Phase Offset: ±15 psLow Static Phase Offset: ±50 psDistributes One Differential Clock Input to Ten Differential Outputs52-Ball µBGA (MicroStar™ Junior BGA, 0,65-mm pitch) and 40-Pin MLFExternal Feedback Pins (FBIN,FBIN) are Used to Synchronize the Outputs to the Input ClocksMeets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300Fail-Safe InputsMicroStar is a trademark of Texas Instruments.1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) ApplicationsSpread Spectrum Clock CompatibleOperating Frequency: 10 MHz to 400 MHzLow Current Consumption: <135 mALow Jitter (Cycle-Cycle): ±30 psLow Output Skew: 35 psLow Period Jitter: ±20 psLow Dynamic Phase Offset: ±15 psLow Static Phase Offset: ±50 psDistributes One Differential Clock Input to Ten Differential Outputs52-Ball µBGA (MicroStar™ Junior BGA, 0,65-mm pitch) and 40-Pin MLFExternal Feedback Pins (FBIN,FBIN) are Used to Synchronize the Outputs to the Input ClocksMeets or Exceeds JESD82-8 PLL Standard for PC2-3200/4300Fail-Safe InputsMicroStar is a trademark of Texas Instruments.

Description

The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to ten differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDDis grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK,CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN,FBIN) and the clock input pair (CK,CK) within the specified stabilization time. The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C. The CDCU877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock input pair (CK,CK) to ten differential pairs of clock outputs (Yn,Yn) and to one differential pair of feedback clock outputs (FBOUT,FBOUT). The clock outputs are controlled by the input clocks (CK,CK), the feedback clocks (FBIN,FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running. When AVDDis grounded, the PLL is turned off and bypassed for test purposes. When both clock inputs (CK,CK) are logic low, the device enters in a low power mode. An input logic detection circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the PLL obtains phase lock between the feedback clock pair (FBIN,FBIN) and the clock input pair (CK,CK) within the specified stabilization time. The CDCU877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from -40°C to 85°C.