C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation; andsensing and signal processing. To accelerate application development, theDigitalPower software development kit (SDK) for C2000 MCUsand theMotorControl software development kit (SDK) for C2000™ MCUsare available. The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200MHz of signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex math operations common in encoded applications. The F2837xS microcontroller family features a CLA real-time control coprocessor. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC) and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for code protection. Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals. Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F2837xS. The uPP interface is a new feature of the C2000™ MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application. Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check outThe Essential Guide for Developing With C2000™ Real-Time Microcontrollersand visit theC2000™ real-time control MCUspage. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out theTMDSCNCD28379DorLAUNCHXL-F28379Devaluation board sand downloadC2000Ware. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The TMS320F2837xS is a powerful 32-bit floating-point microcontroller unit (MCU) designed for advanced closed-loop control applications such asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation; andsensing and signal processing. To accelerate application development, theDigitalPower software development kit (SDK) for C2000 MCUsand theMotorControl software development kit (SDK) for C2000™ MCUsare available. The real-time control subsystem is based on TI’s 32-bit C28x floating-point CPU, which provides 200MHz of signal processing performance. The C28x CPU is further boosted by the new TMU accelerator, which enables fast execution of algorithms with trigonometric operations common in transforms and torque loop calculations; and the VCU accelerator, which reduces the time for complex math operations common in encoded applications. The F2837xS microcontroller family features a CLA real-time control coprocessor. The CLA is an independent 32-bit floating-point processor that runs at the same speed as the main CPU. The CLA responds to peripheral triggers and executes code concurrently with the main C28x CPU. This parallel processing capability can effectively double the computational performance of a real-time control system. By using the CLA to service time-critical functions, the main C28x CPU is free to perform other tasks, such as communications and diagnostics. The TMS320F2837xS supports up to 1MB (512KW) of onboard flash memory with error correction code (ECC) and up to 164KB (82KW) of SRAM. Two 128-bit secure zones are also available on the CPU for code protection. Performance analog and control peripherals are also integrated on the F2837xS MCU to further enable system consolidation. Four independent 16-bit ADCs provide precise and efficient management of multiple analog signals, which ultimately boosts system throughput. The new sigma-delta filter module (SDFM) works in conjunction with the sigma-delta modulator to enable isolated current shunt measurements. The Comparator Subsystem (CMPSS) with windowed comparators allows for protection of power stages when current limit conditions are exceeded or not met. Other analog and control peripherals include DACs, PWMs, eCAPs, eQEPs, and other peripherals. Peripherals such as EMIFs, CAN modules (ISO 11898-1/CAN 2.0B-compliant), and a new uPP interface extend the connectivity of the F2837xS. The uPP interface is a new feature of the C2000™ MCUs and supports high-speed parallel connection to FPGAs or other processors with similar uPP interfaces. Lastly, a USB 2.0 port with MAC and PHY lets users easily add universal serial bus (USB) connectivity to their application. Want to learn more about features that make C2000 MCUs the right choice for your real-time control system? Check outThe Essential Guide for Developing With C2000™ Real-Time Microcontrollersand visit theC2000™ real-time control MCUspage. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. Ready to get started? Check out theTMDSCNCD28379DorLAUNCHXL-F28379Devaluation board sand downloadC2000Ware. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface. The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTCand DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL) and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core. The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support libraries. The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface. The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. Furthermore, the device includes three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power different sections of the device. The DSP_LDO can provide 1.3 V or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed. To allow for lowest power operation, the programmer can shutdown the internal DSP_LDO cutting power to the DSP core (CVDD) while an external supply provides power to the RTC (CVDDRTCand DVDDRTC). The ANA_LDO is designed to provide 1.3 V to the DSP PLL (VDDA_PLL) and power management circuits (VDDA_ANA). The USB_LDO provides 1.3 V to USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3). The RTC alarm interrupt or the WAKEUP pin can re-enable the internal DSP_LDO and re-apply power to the DSP core. The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support libraries.

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2806x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2806x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000.

The 54CST are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls. The 54CST are based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function calls.

The TMS320C64x™ DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x™ is a code-compatible member of the C6000™ DSP platform. With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x™ DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices. The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller. The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution. TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.Windows is a registered trademark of the Microsoft Corporation.Other trademarks are the property of their respective owners.Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name. The TMS320C64x™ DSPs (including the TMS320C6414T, TMS320C6415T, and TMS320C6416T devices) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320C64x™ (C64x™) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for wireless infrastructure applications. The C64x™ is a code-compatible member of the C6000™ DSP platform. With performance of up to 8000 million instructions per second (MIPS) at a clock rate of 1 GHz, the C64x devices offer cost-effective solutions to high-performance DSP programming challenges. The C64x™ DSPs possess the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x. DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units—two multipliers for a 32-bit result and six arithmetic logic units (ALUs)— with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in key applications and extend the parallelism of the VelociTI™ architecture. The C64x can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 4000 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 8000 MMACS. The C64x DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices. The C6416T device has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP) and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 1/2, 1/3, and 1/4, and flexible polynomials, while generating hard decisions or soft decisions. The TCP operating at CPU clock divided-by-2 can decode up to sixty 384-Kbps or ten 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP/TCP and the CPU are carried out through the EDMA controller. The C64x uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 8-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory or combinations of cache (up to 256K bytes) and mapped memory. The peripheral set includes three multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port [C6415T/C6416T only]; three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI) [C6415T/C6416T only]; a general-purpose input/output port (GPIO) with 16 GPIO pins; and two glueless external memory interfaces (64-bit EMIFA and 16-bit EMIFB), both of which are capable of interfacing to synchronous and asynchronous memories and peripherals. The C64x has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows. debugger interface for visibility into source code execution. TMS320C6000, C64x, and C6000 are trademarks of Texas Instruments.Windows is a registered trademark of the Microsoft Corporation.Other trademarks are the property of their respective owners.Throughout the remainder of this document, the TMS320C6414T, TMS320C6415T, and TMS320C6416T shall be referred to as TMS320C64x or C64x where generic, and where specific, their individual full device part numbers will be used or abbreviated as C6414T, C6415T, or C6416T.These C64x™ devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). The prefix "A" in front of a signal name indicates it is an EMIFA signal whereas a prefix "B" in front of a signal name indicates it is an EMIFB signal. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix "A" or "B" may be omitted from the signal name.

The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C2834x (C2834x) Delfino™ microcontroller unit (MCU) devices build on TI’s existing F2833x high-performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point performance, and has up to 516KB of on-chip RAM. Designed for real-time control applications, the C2834x is based on the C28x core, making it code-compatible with all C28x microcontrollers. The on-chip peripherals and low-latency core make the C2834x an excellent solution for performance-hungry real-time control applications. The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and TMS320C28341 devices, members of the Delfino™ MCU generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and C28341, respectively. Device Comparison provides a summary of features for each device. The TMS320C2834x (C2834x) Delfino™ microcontroller unit (MCU) devices build on TI’s existing F2833x high-performance floating-point microcontrollers. The C2834x delivers up to 300 MHz of floating-point performance, and has up to 516KB of on-chip RAM. Designed for real-time control applications, the C2834x is based on the C28x core, making it code-compatible with all C28x microcontrollers. The on-chip peripherals and low-latency core make the C2834x an excellent solution for performance-hungry real-time control applications. The TMS320C28346, TMS320C28345, TMS320C28344, TMS320C28343, TMS320C28342, and TMS320C28341 devices, members of the Delfino™ MCU generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as C28346, C28345, C28344, C28343, C28342, and C28341, respectively. Device Comparison provides a summary of features for each device.

C2000™ real-time control MCUsare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2805x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Analog comparators with internal 6-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. The Analog Front End (AFE) contains up to seven comparators with up to three integrated DACs, one VREFOUT-buffered DAC, up to four PGAs, and up to four digital filters. The PGAs can amplify the input signal in three discrete gain modes. The actual number of AFE peripherals will depend upon the TMS320F2805x device number. See Device Comparison for more details. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage. C2000™ real-time control MCUsare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2805x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Analog comparators with internal 6-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. The Analog Front End (AFE) contains up to seven comparators with up to three integrated DACs, one VREFOUT-buffered DAC, up to four PGAs, and up to four digital filters. The PGAs can amplify the input signal in three discrete gain modes. The actual number of AFE peripherals will depend upon the TMS320F2805x device number. See Device Comparison for more details. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage.

TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set. Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution. The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip TMS320DM8127 DaVinci Digital Media processors are highly integrated, programmable platforms that leverage the technology to meet the processing needs of the following applications to name a few:IP Network Cameras Industrial Automation Network Cameras Stereo Cameras Video Surveillance HD Video Conferencing Car Black BoxHome Audio and Video Equipment The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device also combines programmable video and audio processing with a highly integrated peripheral set. Programmability is provided by an ARM Cortex-A8 RISC CPU with Neon extension, TI C674x VLIW floating-point DSP core, and high-definition video and imaging coprocessors. The ARM lets developers keep control functions separate from A/V algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software. The ARM Cortex-A8 32-Bit RISC Core with Neon floating-point extension includes: 32KB of Instruction cache; 32KB of Data cache; 256KB of L2 Cache; 48KB of Boot ROM; and 64KB of RAM. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD Video Processing Subsystem Dual Port Gigabit Ethernet MACs (10/100/1000 Mbps) [Ethernet Switch] with MII/RMII/GMII/RGMII and MDIO interface supporting IEEE 1588 Time-Stamping, AVB, and Industrial Ethernet ProtocolsTwo USB ports with integrated 2.0 PHY PCIe x1 GEN2 Compliant interfaceTwo 10-serializer McASP audio serial ports (with DIT mode)Four quad-serilaizer McASP audio serial ports (with DIT mode)One McBSP multichannel buffered serial portSix UARTs with IrDA and CIR supportFour SPI serial interfacesThree MMC/SD/SDIO serial interfacesFour I2C master and slave interfaces Parallel Camera Interface (CAM)Up to 128 General-Purpose I/Os (GPIOs)Eight 32-bit general-purpose timers System watchdog timer Dual DDR2, and DDR3 SDRAM interfacesFlexible 8- or 16-bit asynchronous memory interfaceTwo Controller Area Network (DCAN) modulesSpin LockMailbox The TMS320DM8127 DaVinci Digital Media processors also include a high-definition video and imaging coprocessor 2 (HDVICP2) to off-load many video and imaging processing tasks from the DSP core, making more DSP MIPS available for common video and imaging algorithms. Additionally, the TMS320DM8127 DaVinci Digital Media processors have a complete set of development tools for both the ARM and DSP which include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Microsoft® Windows™ debugger interface for visibility into source code execution. The C674x DSP core is the high-performance floating-point DSP generation in the TMS320C6000 DSP platform and is code-compatible with previous generation C64x Fixed-Point and C67x Floating-Point DSP generation. The C674x Floating-Point DSP processor uses 32KB of L1 program memory with EDC and 32KB of L1 data memory. Up to 32KB of L1P can be configured as program cache. The remaining memory is noncacheable no-wait-state program memory. Up to 32KB of L1D can be configured as data cache. The remaining memory is noncacheable no-wait-state data memory. The DSP has 256KB of L2 RAM with ECC, which can be defined as SRAM, L2 cache, or a combination of both. All C674x L3 and off-chip

The TMS320F2810, TMS320F2811, and TMS320F2812-Q1 devices, members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812-Q1 are abbreviated as F2810, F2811, and F2812-Q1, respectively. F281x denotes all three devices. The TMS320F2810, TMS320F2811, and TMS320F2812-Q1 devices, members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, TMS320F2810, TMS320F2811, and TMS320F2812-Q1 are abbreviated as F2810, F2811, and F2812-Q1, respectively. F281x denotes all three devices.

C28x C2000™ C28x Piccolo™ Microcontroller IC 32-Bit Single-Core 90MHz 128KB (64K x 16) FLASH 80-LQFP (12x12)

The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. The TMS320C64x+™ DSPs (including the TMS320DM6435 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6435 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units–two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6435 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6435 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a configurable video port (VPFE); a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; a multichannel buffered serial port (McBSP); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6435 device includes a Video Processing Subsystem (VPSS) with a configurable video/imaging front-end input peripheral used for video capture. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6435. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6435 and the network. The DM6435 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow DM6435 to easily control peripheral devices and/or communicate with host processors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6435 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage.

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2802x family of microcontrollers provides the power of the C28x core coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2802x family of microcontrollers provides the power of the C28x core coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000.

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2806x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2806x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000.

The TMS320VC5507 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core. The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs. The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included. The 5507 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry‘s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS51™. emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries. The TMS320VC5507 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core. The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs. The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included. The 5507 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry‘s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS51™. emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage.

The TMS320C6678 Multicore Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with eight C66x CorePac DSPs, each core runs at 1.0 to 1.25 GHz enabling up to 10 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6678 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs. The TMS320C6678 Multicore Fixed and Floating Point Digital Signal Processor is based on TI's KeyStone multicore architecture. Integrated with eight C66x CorePac DSPs, each core runs at 1.0 to 1.25 GHz enabling up to 10 GHz. The device supports high-performance signal processing applications such as mission critical, medical imaging, test, and automation. The C6678 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform. With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices. The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals. The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M). These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels - A and B with a 5120-byte capture/display buffer that is splittable between the two channels. For more details on the Video Port peripherals, see theTMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide(literature number SPRU629). The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The VXCO interpolated control port (VIC) provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see theTMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide(literature number SPRU629). The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see theTMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide(literature number SPRU628). The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see theTMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide(literature number SPRU628). The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The TMS320C64x™ DSPs (including the TMS320DM642 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The TMS320DM642 (DM642) device is based on the second-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture (VelociTI.2™) developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x™ is a code-compatible member of the C6000™ DSP platform. With performance of up to 5760 million instructions per second (MIPS) at a clock rate of 720 MHz, the DM642 device offers cost-effective solutions to high-performance DSP programming challenges. The DM642 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x™ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs)- with VelociTI.2™ extensions. The VelociTI.2™ extensions in the eight functional units include new instructions to accelerate the performance in video and imaging applications and extend the parallelism of the VelociTI™ architecture. The DM642 can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2880 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 5760 MMACS. The DM642 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000™ DSP platform devices. The DM642 uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 128-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 128-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of an 2-Mbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: three configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC); a management data input/output (MDIO) module; a VCXO interpolated control port (VIC); one multichannel buffered audio serial port (McASP0); an inter-integrated circuit (I2C) Bus module; two multichannel buffered serial ports (McBSPs); three 32-bit general-purpose timers; a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a peripheral component interconnect (PCI); a 16-pin general-purpose input/output port (GP0) with programmable interrupt/event generation modes; and a 64-bit glueless external memory interface (EMIFA), which is capable of interfacing to synchronous and asynchronous memories and peripherals. The DM642 device has three configurable video port peripherals (VP0, VP1, and VP2). These video port peripherals provide a glueless interface to common video decoder and encoder devices. The DM642 video port peripherals support multiple resolutions and video standards (e. g., CCIR601, ITU-BT.656, BT.1120, SMPTE 125M, 260M, 274M, and 296M). These three video port peripherals are configurable and can support either video capture and/or video display modes. Each video port consists of two channels - A and B with a 5120-byte capture/display buffer that is splittable between the two channels. For more details on the Video Port peripherals, see theTMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide(literature number SPRU629). The McASP0 port supports one transmit and one receive clock zone, with eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The DM642 has sufficient bandwidth to support all 8 serial data pins transmitting a 192-kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP0 transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. McASP0 also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The VXCO interpolated control port (VIC) provides digital-to-analog conversion with resolution from 9-bits to up to 16-bits. The output of the VIC is a single bit interpolated D/A output. For more details on the VIC port, see theTMS320C64x Video Port/VXCO Interpolated Control (VIC) Port Reference Guide(literature number SPRU629). The ethernet media access controller (EMAC) provides an efficient interface between the DM642 DSP core processor and the network. The DM642 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex, with hardware flow control and quality of service (QOS) support. The DM642 EMAC makes use of a custom interface to the DSP core that allows efficient data transmission and reception. For more details on the EMAC, see theTMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide(literature number SPRU628). The management data input/output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. Once a PHY candidate has been selected by the DSP, the MDIO module transparently monitors its link state by reading the PHY status register. Link change events are stored in the MDIO module and can optionally interrupt the DSP, allowing the DSP to poll the link status of the device without continuously performing costly MDIO accesses. For more details on the MDIO, see theTMS320C6000 DSP Ethernet Media Access Controller (EMAC) / Management Data Input/Output (MDIO) Module Reference Guide(literature number SPRU628). The I2C0 port on the TMS320DM642 allows the DSP to easily control peripheral devices, boot from a serial EEPROM, and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices.

TMS320C20x Microcontroller IC 100-LQFP (14x14)

C2xx DSP C2000™ C24x 16-Bit Microcontroller IC 16-Bit 20MHz 32KB (16K x 16) FLASH 132-BQFP (24.13x24.13)

The TMS320F2809, TMS320F2809-Q1, TMS320F2808, TMS320F2808-Q1 TMS320F2806, TMS320F2802, TMS320F2801-Q1, TMS320F28015-Q1, TMS320F28016-Q1, TMS320C2802-Q1, and TMS320C2801 devices, members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, TMS320F2809, TMS320F2809-Q1 TMS320F2808, TMS320F2808-Q1 TMS320F2806, TMS320F2802-Q1, TMS320F2801-Q1, TMS320C2802, TMS320C2801, TMS320F28015-Q1, and TMS320F28016-Q1 are abbreviated as F2809, F2808, F2806, F2802-Q1, F2801-Q1, C2802, C2801, F28015-Q1, and F28016-Q1, respectively. TMS320F28015-Q1 and TMS320F28016-Q1 are abbreviated as F2801x. Device Comparison (100-MHz Devices) and Device Comparison (60-MHz Devices) provide a summary of features for each device. The TMS320F2809, TMS320F2809-Q1, TMS320F2808, TMS320F2808-Q1 TMS320F2806, TMS320F2802, TMS320F2801-Q1, TMS320F28015-Q1, TMS320F28016-Q1, TMS320C2802-Q1, and TMS320C2801 devices, members of the TMS320C28x DSP generation, are highly integrated, high-performance solutions for demanding control applications. Throughout this document, TMS320F2809, TMS320F2809-Q1 TMS320F2808, TMS320F2808-Q1 TMS320F2806, TMS320F2802-Q1, TMS320F2801-Q1, TMS320C2802, TMS320C2801, TMS320F28015-Q1, and TMS320F28016-Q1 are abbreviated as F2809, F2808, F2806, F2802-Q1, F2801-Q1, C2802, C2801, F28015-Q1, and F28016-Q1, respectively. TMS320F28015-Q1 and TMS320F28016-Q1 are abbreviated as F2801x. Device Comparison (100-MHz Devices) and Device Comparison (60-MHz Devices) provide a summary of features for each device.

The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purposeinput/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. The TMS320C64x+™ DSPs (including the TMS320C6424 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The C6424 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital signal processor applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in telecom, audio, and industrial applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The C6424 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The C6424 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space–384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purposeinput/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the C6424 and the network. The C6424 EMAC supports 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow C6424 to easily control peripheral devices and/or communicate with host processors. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The C6424 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

C2000™ real-time microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as F28335, F28334, F28333, F28332, F28235, F28234, and F28232, respectively. F2833x Device Comparison and F2823x Device Comparison provide a summary of features for each device. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage. C2000™ real-time microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as F28335, F28334, F28333, F28332, F28235, F28234, and F28232, respectively. F2833x Device Comparison and F2823x Device Comparison provide a summary of features for each device. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage.

The TMS320C67x™ DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices) compose the floating-point DSP family in the TMS320C6000™ DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of 200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS. The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals. The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution. The TMS320C67x™ DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices) compose the floating-point DSP family in the TMS320C6000™ DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications. With performance of up to 1200 million floating-point operations per second (MFLOPS) at a clock rate of 200 MHz or up to 1500 MFLOPS at a clock rate of 250 MHz, the C6711D device also offers cost-effective solutions to high-performance DSP programming challenges. The C6711D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6711D can produce two MACs per cycle for a total of 400 MMACS. The C6711D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6711D device uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM and asynchronous peripherals. The C6711D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

The TMS320C64x+™ DSPs (including the TMS320DM6437 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6437 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6437 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6437 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6437 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6437. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6437 and the network. The DM6437 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow DM6437 to easily control peripheral devices and/or communicate with host processors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6437 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code The TMS320C64x+™ DSPs (including the TMS320DM6437 device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The DM6437 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for digital media applications. The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The C64x™ DSPs support added functionality and have an expanded instruction set from previous devices. Any reference to the C64x DSP or C64x CPU also applies, unless otherwise noted, to the C64x+ DSP and C64x+ CPU, respectively. With performance of up to 4800 million instructions per second (MIPS) at a clock rate of 600 MHz, the C64x+ core offers solutions to high-performance DSP programming challenges. The DSP core possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. The C64x+ DSP core processor has 64 general-purpose registers of 32-bit word length and eight highly independent functional units-two multipliers for a 32-bit result and six arithmetic logic units (ALUs). The eight functional units include instructions to accelerate the performance in video and imaging applications. The DSP core can produce four 16-bit multiply-accumulates (MACs) per cycle for a total of 2400 million MACs per second (MMACS), or eight 8-bit MACs per cycle for a total of 4800 MMACS. For more details on the C64x+ DSP, see the TMS320C64x/C64x+ DSP CPU and Instruction Set Reference Guide (literature number SPRU732). The DM6437 also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals similar to the other C6000 DSP platform devices. The DM6437 core uses a two-level cache-based architecture. The Level 1 program memory/cache (L1P) consists of a 256K-bit memory space that can be configured as mapped memory or direct mapped cache, and the Level 1 data (L1D) consists of a 640K-bit memory space-384K-bit of which is mapped memory and 256K-bit of which can be configured as mapped memory or 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 1M-bit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes: 2 configurable video ports; a 10/100 Mb/s Ethernet MAC (EMAC) with a management data input/output (MDIO) module; a 4-bit transmit, 4-bit receive VLYNQ interface; an inter-integrated circuit (I2C) Bus interface; two multichannel buffered serial ports (McBSPs); a multichannel audio serial port (McASP0) with 4 serializers; 2 64-bit general-purpose timers each configurable as 2 independent 32-bit timers; 1 64-bit watchdog timer; a user-configurable 16-bit host-port interface (HPI); up to 111-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 2 UARTs with hardware handshaking support on 1 UART; 3 pulse width modulator (PWM) peripherals; 1 high-end controller area network (CAN) controller [HECC]; 1 peripheral component interconnect (PCI) [33 MHz]; and 2 glueless external memory interfaces: an asynchronous external memory interface (EMIFA) for slower memories/peripherals, and a higher speed synchronous memory interface for DDR2. The DM6437 device includes a Video Processing Subsystem (VPSS) with two configurable video/imaging peripherals: 1 Video Processing Front-End (VPFE) input used for video capture, 1 Video Processing Back-End (VPBE) output. The Video Processing Front-End (VPFE) is comprised of a CCD Controller (CCDC), a Preview Engine (Previewer), Histogram Module, Auto-Exposure/White Balance/Focus Module (H3A), and Resizer. The CCDC is capable of interfacing to common video decoders, CMOS sensors, and Charge Coupled Devices (CCDs). The Previewer is a real-time image processing engine that takes raw imager data from a CMOS sensor or CCD and converts from an RGB Bayer Pattern to YUV422. The Histogram and H3A modules provide statistical information on the raw color data for use by the DM6437. The Resizer accepts image data for separate horizontal and vertical resizing from 1/4x to 4x in increments of 256/N, where N is between 64 and 1024. The Video Processing Back-End (VPBE) is comprised of an On-Screen Display Engine (OSD) and a Video Encoder (VENC). The OSD engine is capable of handling 2 separate video windows and 2 separate OSD windows. Other configurations include 2 video windows, 1 OSD window, and 1 attribute window allowing up to 8 levels of alpha blending. The VENC provides four analog DACs that run at 54 MHz, providing a means for composite NTSC/PAL video, S-Video, and/or Component video output. The VENC also provides up to 24 bits of digital output to interface to RGB888 devices. The digital output is capable of 8/16-bit BT.656 output and/or CCIR.601 with separate horizontal and vertical syncs. The Ethernet Media Access Controller (EMAC) provides an efficient interface between the DM6437 and the network. The DM6437 EMAC support both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode, with hardware flow control and quality of service (QOS) support. The Management Data Input/Output (MDIO) module continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system. The I2C and VLYNQ ports allow DM6437 to easily control peripheral devices and/or communicate with host processors. The high-end controller area network (CAN) controller [HECC] module provides a network protocol in a harsh environment to communicate serially with other controllers, typically in automotive applications. The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides. The DM6437 has a complete set of development tools. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code

The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform. The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform. The TMS320C64x+ DSPs (including the TMS320C6474 device) are the highest-performance multicore DSP generation in the TMS320C6000™ DSP platform. The C6474 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI). The C64x+™ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

C28x C2000™ C28x Delfino™, Functional Safety (FuSa) Microcontroller IC 32-Bit Single-Core 200MHz 512KB (256K x 16) FLASH 176-HLQFP (24x24)

C28x C2000™ C28x Piccolo™ Microcontroller IC 32-Bit Single-Core 60MHz 32KB (16K x 16) FLASH 80-LQFP (12x12)

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage.

Developers can now deliver crystal clear multi-format video at up to 1080p H.264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM368 DaVinci™ video processors from Texas Instruments Incorporated (TI). The DM368 is capable of achieving HD video processing at 1080p 30fps H.264 and is completely pin-to-pin compatible with the DM365 processors, using the same ARM926EJ-S core running at 432 MHz. This ARM9-based DM368 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This allows developers to obtain optimal performance from the ARM for their applications, including their multi-channel, multi-stream and multi-format needs. Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can take advantage of the low power consumption and can ensure interoperability, as well as product scalability by taking advantage of the full suite of codecs supported on the DM368. Along with multi-format HD video, the DM368 also features a suite of peripherals saving developers on system cost and complexity to enable a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.565, BT1120. The DM368 also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to digital converter and many more features saving developers on overall system costs, as well as real estate on their circuit boards allowing for a slimmer, sleeker design. Developers can now deliver crystal clear multi-format video at up to 1080p H.264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM368 DaVinci™ video processors from Texas Instruments Incorporated (TI). The DM368 is capable of achieving HD video processing at 1080p 30fps H.264 and is completely pin-to-pin compatible with the DM365 processors, using the same ARM926EJ-S core running at 432 MHz. This ARM9-based DM368 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG and VC1/WMV9 codecs providing customers with the flexibility to select the right video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This allows developers to obtain optimal performance from the ARM for their applications, including their multi-channel, multi-stream and multi-format needs. Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players and more can take advantage of the low power consumption and can ensure interoperability, as well as product scalability by taking advantage of the full suite of codecs supported on the DM368. Along with multi-format HD video, the DM368 also features a suite of peripherals saving developers on system cost and complexity to enable a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.565, BT1120. The DM368 also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to digital converter and many more features saving developers on overall system costs, as well as real estate on their circuit boards allowing for a slimmer, sleeker design.

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2806x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2806x family of microcontrollers (MCUs) provides the power of the C28x core and CLA coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the ePWM outputs. The ADC converts from 0 to 3.3-V fixed full-scale range and supports ratio-metric VREFHI/VREFLOreferences. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit the C2000 Overview atwww.ti.com/c2000.

C28x C2000™ C28x Fixed-Point Microcontroller IC 32-Bit Single-Core 150MHz ROMless 179-BGA MicroStar (12x12)

The TMS320C6670 Multicore Fixed and Floating Point System on Chip is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance applications such as software defined radio, emerging broadband and other communications segments. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.20 GHz enabling up to 4.8 GHz. Hardware acceleration provides a highly integrated, power efficient and easy to use platform for implementing a combination of multi-band, multi-standard waveforms, including proprietary air-interfaces. The C6670 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs. The TMS320C6670 Multicore Fixed and Floating Point System on Chip is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance applications such as software defined radio, emerging broadband and other communications segments. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.20 GHz enabling up to 4.8 GHz. Hardware acceleration provides a highly integrated, power efficient and easy to use platform for implementing a combination of multi-band, multi-standard waveforms, including proprietary air-interfaces. The C6670 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

The TMS320C67x™ DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS). The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM. The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see thebootmodesection of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™ kernel. The TMS320C67x™ DSPs (including the TMS320C6713B device) compose the floating-point DSP generation in the TMS320C6000™ DSP platform. The C6713B device is based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making this DSP an excellent choice for multichannel and multifunction applications. Operating at 225 MHz, the C6713B delivers up to 1350 million floating-point operations per second (MFLOPS), 1800 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 450 million multiply-accumulate operations per second (MMACS). Operating at 300 MHz, the C6713B delivers up to 1800 million floating-point operations per second (MFLOPS), 2400 million instructions per second (MIPS), and with dual fixed-/floating-point multipliers up to 600 million multiply-accumulate operations per second (MMACS). The C6713B uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 4K-byte direct-mapped cache and the Level 1 data cache (L1D) is a 4K-byte 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 256K-byte memory space that is shared between program and data space. 64K bytes of the 256K bytes in L2 memory can be configured as mapped memory, cache, or combinations of the two. The remaining 192K bytes in L2 serves as mapped SRAM. The C6713B has a rich peripheral set that includes two Multichannel Audio Serial Ports (McASPs), two Multichannel Buffered Serial Ports (McBSPs), two Inter-Integrated Circuit (I2C) buses, one dedicated General-Purpose Input/Output (GPIO) module, two general-purpose timers, a host-port interface (HPI), and a glueless external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The two McASP interface modules each support one transmit and one receive clock zone. Each of the McASP has eight serial data pins which can be individually allocated to any of the two zones. The serial port supports time-division multiplexing on each pin from 2 to 32 time slots. The C6713B has sufficient bandwidth to support all 16 serial data pins transmitting a 192 kHz stereo signal. Serial data in each zone may be transmitted and received on multiple serial data pins simultaneously and formatted in a multitude of variations on the Philips Inter-IC Sound (I2S) format. In addition, the McASP transmitter may be programmed to output multiple S/PDIF, IEC60958, AES-3, CP-430 encoded data channels simultaneously, with a single RAM containing the full implementation of user data and channel status fields. The McASP also provides extensive error-checking and recovery features, such as the bad clock detection circuit for each high-frequency master clock which verifies that the master clock is within a programmed frequency range. The two I2C ports on the TMS320C6713B allow the DSP to easily control peripheral devices and communicate with a host processor. In addition, the standard multichannel buffered serial port (McBSP) may be used to communicate with serial peripheral interface (SPI) mode peripheral devices. The TMS320C6713B device has two bootmodes: from the HPI or from external asynchronous ROM. For more detailed information, see thebootmodesection of this data sheet. The TMS320C67x DSP generation is supported by the TI eXpressDSP™ set of industry benchmark development tools, including a highly optimizing C/C++ Compiler, the Code Composer Studio™ Integrated Development Environment (IDE), JTAG-based emulation and real-time debugging, and the DSP/BIOS™ kernel.

C2000™ real-time microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as F28335, F28334, F28333, F28332, F28235, F28234, and F28232, respectively. F2833x Device Comparison and F2823x Device Comparison provide a summary of features for each device. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage. C2000™ real-time microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The TMS320F28335, TMS320F28334, TMS320F28333, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices are highly integrated, high-performance solutions for demanding control applications. Throughout this document, the devices are abbreviated as F28335, F28334, F28333, F28332, F28235, F28234, and F28232, respectively. F2833x Device Comparison and F2823x Device Comparison provide a summary of features for each device. TheGetting Started With C2000™ Real-Time Control Microcontrollers (MCUs) Getting Started Guidecovers all aspects of development with C2000 devices from hardware to support resources. In addition to key reference documents, each section provides relevant links and resources to further expand on the information covered. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage.

The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5416 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls. The TMS320VC5416 fixed-point, digital signal processor (DSP) (hereafter referred to as the 5416 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The device also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage. C2000™ 32-bit microcontrollersare optimized for processing, sensing, and actuation to improve closed-loop performance inreal-time control applicationssuch asindustrial motor drives;solar inverters and digital power;electrical vehicles and transportation;motor control; andsensing and signal processing. The C2000 line includes thePremium performance MCUsand theEntry performance MCUs. The F2803x family of microcontrollers provides the power of the C28x core and Control Law Accelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, and also provides a high level of analog integration. An internal voltage regulator allows for single-rail operation. Enhancements have been made to the HRPWM to allow for dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3V fixed full-scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead and latency. To learn more about the C2000 MCUs, visit theC2000™ real-time control MCUspage.

The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface. The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL).Note:ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL). The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support libraries. The device is a member of TI's TMS320C5000™ fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. The fixed-point DSP is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16-independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity. The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU. The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to the Address Unit (AU) and Data Unit (DU) resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions. Serial media is supported through two MultiMedia Card/Secure Digital (MMC/SD) peripherals, four Inter-IC Sound (I2S Bus™) modules, one Serial-Port Interface (SPI) with up to 4 chip selects, one I2C multi-master and slave interface, and a Universal Asynchronous Receiver/Transmitter (UART) interface. The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM). Additional peripherals include: a high-speed Universal Serial Bus (USB2.0) device mode only, and a real-time clock (RTC). This device also includes three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator. The device includes one integrated LDO (ANA_LDO) to provide regulated 1.3 V to the DSP PLL (VDDA_PLL).Note:ANA_LDO can only provide a regulated 1.3 V. When the DSP PLL requires 1.4 V (PLLOUT > 120 MHz), an external supply is required to supply 1.4 V to the DSP PLL (VDDA_PLL). The device is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry’s largest third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX™, XDS100™, XDS510™, XDS560™ emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, and various math functions) as well as chip support libraries.