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TMS320C6670AXCYPA2 - FCBGA (CYP)

TMS320C6670AXCYPA2

Active
Texas Instruments

4 CORE FIXED AND FLOATING POINT DSP FOR COMMUNICATIONS AND TELECOM

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsKeyStone I DDR3 Initialization (Rev. E)Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)+66
TMS320C6670AXCYPA2 - FCBGA (CYP)

TMS320C6670AXCYPA2

Active
Texas Instruments

4 CORE FIXED AND FLOATING POINT DSP FOR COMMUNICATIONS AND TELECOM

Deep-Dive with AI

DocumentsKeyStone I DDR3 Initialization (Rev. E)Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)+66

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 2$ 307.44
Texas InstrumentsJEDEC TRAY (5+1) 1$ 248.67
100$ 225.09
250$ 218.66
1000$ 214.37

Description

General part information

TMS320 Series

The TMS320C6670 Multicore Fixed and Floating Point System on Chip is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance applications such as software defined radio, emerging broadband and other communications segments. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.20 GHz enabling up to 4.8 GHz. Hardware acceleration provides a highly integrated, power efficient and easy to use platform for implementing a combination of multi-band, multi-standard waveforms, including proprietary air-interfaces. The C6670 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

The TMS320C6670 Multicore Fixed and Floating Point System on Chip is a member of the C66xx SoC family based on TI's new KeyStone Multicore SoC Architecture designed specifically for high performance applications such as software defined radio, emerging broadband and other communications segments. Integrated with four C66x CorePac DSPs, each core runs at 1.0 to 1.20 GHz enabling up to 4.8 GHz. Hardware acceleration provides a highly integrated, power efficient and easy to use platform for implementing a combination of multi-band, multi-standard waveforms, including proprietary air-interfaces. The C6670 platform is power efficient and easy to use. The C66x CorePac DSP is fully backward compatible with all existing C6000 family of fixed and floating point DSPs.

Documents

Technical documentation and resources

KeyStone I DDR3 Initialization (Rev. E)

Application note

Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)

User guide

Keystone Multicore Device Family Schematic Checklist

Application note

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

User guide

TI Keystone DSP Hyperlink SerDes IBIS-AMI Models

Application note

A Diverse High Performance Platform for Advanced Driver Assistance System

White paper

KeyStone Multicore SoC Tool Suite: one platform for all needs

White paper

Connecting AIF to FFTC Guide for KeyStone Devices

Application note

Migrating From AIF1 to AIF2 for KeyStone Devices

Application note

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

User guide

Clocking Design Guide for KeyStone Devices

Application note

TMS320C66x DSP Generation of Devices (Rev. A)

Application note

TMS320C6670 Breakthrough Performance for Process-Intensive Applications (Rev. B)

Product overview

C66x DSP Cache User's Guide

User guide

Viterbi-Decoder Coprocessor 2 (VCP2) for KeyStone Devices User's Guide (Rev. A)

User guide

Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A)

User guide

Maximizing Multicore Efficiency with Navigator Runtime

White paper

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

User guide

Multicore Programming Guide (Rev. B)

Application note

TMS320C6000 Optimizing Compiler v 7.4 User's Guide (Rev. U)

User guide

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

User guide

Network Coprocessor for KeyStone Devices User's Guide

User guide

Antenna Interface 2 (AIF2) for KeyStone I Devices User's Guide (Rev. E)

User guide

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

User guide

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

User guide

SerDes Implementation Guidelines for KeyStone I Devices

Application note

Turbo Decoder Coprocessor 3 (TCP3D) for KeyStone Devices User's Guide

User guide

Keystone Error Detection and Correction EDC ECC (Rev. A)

Application note

TMS320C6670 Multicore Fixed and Floating-Point System-on-Chip datasheet (Rev. D)

Data sheet

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

User guide

C66x CPU and Instruction Set Reference Guide

User guide

DDR3 Design Requirements for KeyStone Devices (Rev. D)

Application note

C66x CorePac User's Guide (Rev. C)

User guide

System Analyzer User's Guide (Rev. F)

User guide

How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)

Application note

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

User guide

PCIe Use Cases for KeyStone Devices

Application note

TMS320C6670 Multicore Fixed and Floating-Point SoC Errata (Revision 1.0, 2.0) (Rev. F)

Errata

Keystone NDK FAQ

Application note

Introduction to TMS320C6000 DSP Optimization

Application note

HyperLink for KeyStone Devices User's Guide (Rev. C)

User guide

Tuning VCP2 and TCP2 Bit Error Rate Performance

Application note

TMS320C6000 Assembly Language Tools v 7.4 User's Guide (Rev. W)

User guide

KeyStone Memory Architecture White Paper (Rev. A)

White paper

SYS/BIOS (TI-RTOS Kernel) User's Guide (Rev. V)

User guide

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG

User guide

SERDES Link Commissioning on KeyStone I and II Devices

Application note

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

User guide

Accelerating high-performance computing development with Desktop Linux SDK

White paper

Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)

User guide

Turbo Encoder Coprocessor 3 (TCP3E) for KeyStone Devices User's Guide

User guide

Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide (Rev. A)

User guide

KeyStone Lab Manual - Training

More literature

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

Application note

Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)

User guide

Fast Fourier Transform Coprocessor (FFTC) for KeyStone Devices User's Guide (Rev. C)

User guide

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

User guide

PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)

User guide

Keystone Bootloader Resources and FAQ

Application note

Debug and Trace for KeyStone I Devices User's Guide (Rev. A)

User guide

DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)

User guide

Multicore SoCs stay a step ahead of SoC FPGAs

White paper

DDR3 Memory Controller for KeyStone I Devices User's Guide (Rev. E)

User guide

Optimizing Loops on the C66x DSP

Application note

Hardware Design Guide for KeyStone Devices (Rev. D)

Application note

Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D)

User guide

TI Keystone DSP PCIe SerDes IBIS-AMI Models

Application note

Bit Rate Coprocessor (BCP) for KeyStone Devices User's Guide (Rev. A)

User guide