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TMS320VC5502PGF200 - LQFP (PGF)

TMS320VC5502PGF200

Active
Texas Instruments

FIXED-POINT DIGITAL SIGNAL PROCESSOR

TMS320VC5502PGF200 - LQFP (PGF)

TMS320VC5502PGF200

Active
Texas Instruments

FIXED-POINT DIGITAL SIGNAL PROCESSOR

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 12.70
10$ 11.68
40$ 11.19
80$ 9.86
240$ 9.38
440$ 8.77
960$ 8.05
Texas InstrumentsJEDEC TRAY (5+1) 1$ 9.94
100$ 8.69
250$ 6.70
1000$ 5.99

Description

General part information

TMS320 Series

The TMS320VC5502 (5502) fixed-point digital signal processor (DSP) is based on the TMS320C55x™ DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform data transfers independent of the CPU activity.

The C55x™ CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

Documents

Technical documentation and resources

TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (Rev. L)

Errata

TMS320VC5502 to TMS320C5517 Hardware Migration Guide

Application note

TMS320VC5501/5502 DSP Direct Memory Access (DMA) Controller Reference Guide (Rev. G)

User guide

Migrating from TMS320VC5402A to TMS320VC5502

Application note

Migrating from TMS320VC5510 to TMS320VC5502

Application note

TMS320VC5501/5502/5503/5507/5509/5510 DSP (McBSP) Reference Guide (Rev. E)

User guide

TMS320VC5501/5502/5503/5507/5509 DSP Inter-Integrated Circuit (I2C) Module RG (Rev. D)

User guide

TMS320C55x DSP CPU Programmer's Reference Supplement (Rev. G)

User guide

TMS320VC5501/5502 DSP Universal Asynchronous Receiver/Transmitter (UART) RG (Rev. B)

User guide

TMS320VC5501/VC5502 MicroStar BGA Discontinued and Redesigned

Errata

TMS320VC5501, TMS320VC5502 Power Consumption Summary (Rev. A)

Application note

TMS320VC5501/5502 DSP Instruction Cache Reference Guide (Rev. C)

User guide

TMS320C55x DSP Mnemonic Instruction Set Reference Guide (Rev. G)

User guide

TMS320VC5502 Hardware Designer's Resource Guide

Application note

TMS320VC5501/5502 DSP Host Port Interface (HPI) Reference Guide (Rev. D)

User guide

Achieving Efficient Memory System Performance w/ I-Cache on the TMS320VC5501/02 (Rev. A)

Application note

Using the TMS320VC5501/5502 Bootloader (Rev. C)

Application note

TMS320VC5501/5502 DSP Timers Reference Guide (Rev. B)

User guide

TMS320VC5502 Fixed-Point Digital Signal Processor datasheet (Rev. K)

Data sheet

TMS320VC5501/5502 DSP External Memory Interface (EMIF) Reference Guide (Rev. F)

User guide

TMS320C55x DSP Peripherals Overview Reference Guide (Rev. K)

User guide

TMS320C55x DSP CPU Reference Guide (Rev. F)

User guide

TMS320C55x Chip Support Library API Reference Guide (Rev. J)

User guide