Texas Instruments

The CD54HC646 and CD74HCT646 consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus is clocked into the registers on the low-to-high transition of the... Read More

The CD74HC652 and CD74HCT652 three-state, octal-bus transceiver/registers use silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. The CD74HC652 and CD74HCT652 have non-inverting outputs. These devices consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed... Read More

The ’HC670 and CD74HCT670 are 16-bit register files organized as 4 words x 4 bits each. Read and write address and enable inputs allow simultaneous writing into one location while reading another. Four data inputs are provided to store the 4-bit word. The write address inputs (WA0 and WA1) determine... Read More

8-Bit Identity/Magnitude Comparators (P=Q) with Enable

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector... Read More

High speed CMOS logic dual negative-edge-triggered J-K flip-flops with reset

The CDx4HCT74-Q1 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each. The CDx4HCT74-Q1 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each.

The ’HC75 and ’HCT75 are dual 2-bit bistable transparent latches. Each one of the 2-bit latches is controlled by separate Enable inputs (1E\ and 2E\) which are active LOW. When the Enable input is HIGH data enters the latch and appears at the Q output. When the Enable input (1E\... Read More

4-Bit Magnitude Comparator

This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic. This device contains four independent 2-input XOR gates. Each gate performs the Boolean function Y = A ⊕ B in positive logic.

High Speed CMOS Logic 4-Bit Binary Ripple Counter

The CD74HCU04 unbuffered hex inverter utilizes silicon-gate CMOS technology to achieve operation speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. These devices are especially useful in crystal oscillator and analog applications. The CD74HCU04 unbuffered hex inverter utilizes silicon-gate CMOS technology to achieve operation... Read More

The CD74HCU04-Q1 device contains six independent high-speed CMOS unbuffered inverters. Each inverter performs the Boolean function Y =Ain positive logic. The CD74HCU04-Q1 device contains six independent high-speed CMOS unbuffered inverters. Each inverter performs the Boolean function Y =Ain positive logic.

The CDC1104 is a 1 to 4 configurable clock buffer. The device accepts an input reference clock and creates 4 buffered output clocks with an output frequency equal to one half the input clock frequency. Four control inputs, S1, S2, S3, S4 configurable phases of the clock outputs. The CDC1104... Read More

The CDC203 contains six independent inverters. The device performs the Boolean function Y = A\. It is designed specifically for applications requiring low skew between switching outputs. The CDC203 is characterized for operation from 25°C to 70°C. The CDC203 contains six independent inverters. The device performs the Boolean function Y... Read More

The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to... Read More

The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE\) input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351... Read More

The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to 10 outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351... Read More

The CDC2351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE\) input disables the outputs to a high-impedance state. Each output has an internal series damping resistor to improve signal integrity at the load. The CDC2351... Read More

The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC.... Read More