CD74HCT74 Series

High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset

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Catalog

High Speed CMOS Logic Dual Positive-Edge-Triggered D Flip-Flops with Set and Reset

Part	Clock Frequency	Type	Number of Bits per Element	Current - Quiescent (Iq)	Max Propagation Delay @ V, Max CL	Package / Case	Package / Case	Package / Case	Current - Output High, Low	Trigger Type	Input Capacitance	Output Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Function	Number of Elements [custom]	Operating Temperature [Min]	Operating Temperature [Max]
Texas Instruments CD74HCT74M96	50 MHz	D-Type	1	4 çA	35 ns	3.9 mm	0.154 in	14-SOIC	4 mA, 4 mA	Positive Edge	10 pF	Complementary	5.5 V	4.5 V	Surface Mount	Reset, Set(Preset)	2	-55 C	125 °C
Texas Instruments CD74HCT74MT	50 MHz	D-Type	1	4 çA	35 ns	3.9 mm	0.154 in	14-SOIC	4 mA, 4 mA	Positive Edge	10 pF	Complementary	5.5 V	4.5 V	Surface Mount	Reset, Set(Preset)	2	-55 C	125 °C
Texas Instruments CD74HCT74M	50 MHz	D-Type	1	4 çA	35 ns	3.9 mm	0.154 in	14-SOIC	4 mA, 4 mA	Positive Edge	10 pF	Complementary	5.5 V	4.5 V	Surface Mount	Reset, Set(Preset)	2	-55 C	125 °C
Texas Instruments CD74HCT74E	50 MHz	D-Type	1	4 çA	35 ns	7.62 mm	0.3 in	14-DIP	4 mA, 4 mA	Positive Edge	10 pF	Complementary	5.5 V	4.5 V	Through Hole	Reset, Set(Preset)	2	-55 C	125 °C
Texas Instruments CD74HCT74M96G4	50 MHz	D-Type	1	4 çA	35 ns	3.9 mm	0.154 in	14-SOIC	4 mA, 4 mA	Positive Edge	10 pF	Complementary	5.5 V	4.5 V	Surface Mount	Reset, Set(Preset)	2	-55 C	125 °C

Key Features

• LSTTL input logic compatibleVIL(max)= 0.8 V, VIH(min)= 2 VCMOS input logic compatibleII≤ 1 µA at VOL, VOHBuffered inputs4.5 V to 5.5 V operationWide operating temperature range: -55°C to +125°CSupports fanout up to 10 LSTTL loadsSignificant power reduction compared to LSTTL logic ICsLSTTL input logic compatibleVIL(max)= 0.8 V, VIH(min)= 2 VCMOS input logic compatibleII≤ 1 µA at VOL, VOHBuffered inputs4.5 V to 5.5 V operationWide operating temperature range: -55°C to +125°CSupports fanout up to 10 LSTTL loadsSignificant power reduction compared to LSTTL logic ICs

Description

The CDx4HCT74-Q1 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each. The CDx4HCT74-Q1 devices contain two independent D-type positive-edge-triggered flip-flops with asynchronous preset and clear pins for each.