CDC2509 Series

1-to-9 PLL clock driver for SDRAM applications

Link to Manufacturer Page: https://www.ti.com/

Catalog

1-to-9 PLL clock driver for SDRAM applications

Part	Mounting Type	Package / Case [y]	Package / Case [y]	Package / Case	Number of Circuits	Supplier Device Package	Output	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	PLL	Voltage - Supply [Max]	Voltage - Supply [Min]	Frequency - Max [Max]	Operating Temperature [Max]	Type
Texas Instruments CDC2509CPW	Surface Mount	4.4 mm	0.173 "	24-TSSOP	1	24-TSSOP	LVTTL	1	9	Yes with Bypass	3.6 V	3 V	125 MHz	85 °C	PLL Clock Driver
Texas Instruments CDC2509BPW	Surface Mount	4.4 mm	0.173 "	24-TSSOP	1	24-TSSOP	LVTTL	1	9	Yes with Bypass	3.6 V	3 V	125 MHz	70 ░C	PLL Clock Driver
Texas Instruments CDC2509PWR	Surface Mount	4.4 mm	0.173 "	24-TSSOP	1	24-TSSOP	LVTTL	1	9	Yes with Bypass	3.6 V	3 V	125 MHz	70 ░C	PLL Clock Driver
Texas Instruments CDC2509APWR	Surface Mount	4.4 mm	0.173 "	24-TSSOP	1	24-TSSOP	LVTTL	1	9	Yes with Bypass	3.6 V	3 V		70 ░C	PLL Clock Driver
Texas Instruments CDC2509CPWR	Surface Mount	4.4 mm	0.173 "	24-TSSOP	1	24-TSSOP	LVTTL	1	9	Yes with Bypass	3.6 V	3 V	125 MHz	85 °C	PLL Clock Driver
Texas Instruments CDC2509BPWR	Surface Mount	4.4 mm	0.173 "	24-TSSOP	1	24-TSSOP	LVTTL	1	9	Yes with Bypass	3.6 V	3 V	125 MHz	70 ░C	PLL Clock Driver

Key Features

• Use CDCVF2510A as a Replacement for this DeviceDesigned to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2Spread Spectrum Clock CompatibleOperating Frequency 25 MHz to 125 MHzStatic tPhase Error Distribution at 66MHz to 100 MHz is ±150 psDrop-In Replacement for TI CDC2509A With Enhanced PerformanceJitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|Available in Plastic 24-Pin TSSOPPhase-Lock Loop Clock Distribution for Synchronous DRAM ApplicationsDistributes One Clock Input to One Bank of Five and One Bank of Four OutputsSeparate Output Enable for Each Output BankExternal Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock InputOn-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 VUse CDCVF2510A as a Replacement for this DeviceDesigned to Meet PC SDRAM Registered DIMM Design Support Document Rev. 1.2Spread Spectrum Clock CompatibleOperating Frequency 25 MHz to 125 MHzStatic tPhase Error Distribution at 66MHz to 100 MHz is ±150 psDrop-In Replacement for TI CDC2509A With Enhanced PerformanceJitter (cyc - cyc) at 66 MHz to 100 MHz is |100 ps|Available in Plastic 24-Pin TSSOPPhase-Lock Loop Clock Distribution for Synchronous DRAM ApplicationsDistributes One Clock Input to One Bank of Five and One Bank of Four OutputsSeparate Output Enable for Each Output BankExternal Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock InputOn-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 V

Description

The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground. The CDC2509C is characterized for operation from 0°C to 85°C. For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039). The CDC2509C is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDC2509C operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDC2509C does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDC2509C requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground. The CDC2509C is characterized for operation from 0°C to 85°C. For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039).