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CDC208 Series

5-V dual 1-to-4 clock driver

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

5-V dual 1-to-4 clock driver

PartNumber of CircuitsInputVoltage - Supply [Max]Voltage - Supply [Min]Mounting TypeOutputTypeOperating Temperature [Min]Operating Temperature [Max]Frequency - Max [Max]Ratio - Input:Output [custom]Ratio - Input:Output [custom]Package / CasePackage / CaseDifferential - Input:Output [custom]Differential - Input:Output [custom]Supplier Device Package
Texas Instruments
CDC208DW
2
TTL
5.5 V
4.5 V
Surface Mount
CMOS
Fanout Buffer (Distribution)
-40 °C
85 °C
60 MHz
4
1
0.295 in, 7.5 mm
20-SOIC
20-SOIC
Texas Instruments
CDC208DWR
2
TTL
5.5 V
4.5 V
Surface Mount
CMOS
Fanout Buffer (Distribution)
-40 °C
85 °C
60 MHz
4
1
0.295 in, 7.5 mm
20-SOIC
20-SOIC
Texas Instruments
CDC208DWRG4
2
TTL
5.5 V
4.5 V
Surface Mount
CMOS
Fanout Buffer (Distribution)
-40 °C
85 °C
60 MHz
4
1
0.295 in, 7.5 mm
20-SOIC
20-SOIC
Texas Instruments
CDC208NSRG4
2
TTL
5.5 V
4.5 V
Surface Mount
CMOS
Fanout Buffer (Distribution)
-40 °C
85 °C
60 MHz
4
1
0.209 in, 5.3 mm
20-SOIC
20-SO
Texas Instruments
CDC208-7DW
Texas Instruments
CDC208NS
2
TTL
5.5 V
4.5 V
Surface Mount
CMOS
Fanout Buffer (Distribution)
-40 °C
85 °C
60 MHz
4
1
0.209 in, 5.3 mm
20-SOIC
20-SO
Texas Instruments
CDC208DBR
Texas Instruments
CDC208NSG4
2
TTL
5.5 V
4.5 V
Surface Mount
CMOS
Fanout Buffer (Distribution)
-40 °C
85 °C
60 MHz
4
1
0.209 in, 5.3 mm
20-SOIC
20-SO

Key Features

• Low-Skew Propagation Delay Specifications for Clock-Driver ApplicationsTTL-Compatible Inputs and CMOS-Compatible OutputsFlow-Through Architecture OptimizesPCB LayoutCenter-Pin VCCand GND Pin Configurations Minimize High-Speed Switching NoiseEPICTM(Enhanced-Performance Implanted CMOS) 1-um Process500-mA Typical Latch-Up Immunity at 125°CPackage Options Include Plastic Small-Outline (DW)EPIC is a trademark of Texas Instruments Incorporated.Low-Skew Propagation Delay Specifications for Clock-Driver ApplicationsTTL-Compatible Inputs and CMOS-Compatible OutputsFlow-Through Architecture OptimizesPCB LayoutCenter-Pin VCCand GND Pin Configurations Minimize High-Speed Switching NoiseEPICTM(Enhanced-Performance Implanted CMOS) 1-um Process500-mA Typical Latch-Up Immunity at 125°CPackage Options Include Plastic Small-Outline (DW)EPIC is a trademark of Texas Instruments Incorporated.

Description

AI
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input. Skew parameters are specified for a reduced temperature and voltage range common to many applications. The CDC208 is characterized for operation from -40°C to 85°C. The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew for clock distribution (see Figure 2). The device also offers two output-enable (OE1\ and OE2\) inputs for each circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level independent of the signal on the respective A input. Skew parameters are specified for a reduced temperature and voltage range common to many applications. The CDC208 is characterized for operation from -40°C to 85°C.