CDCVF2505PW
ActivePLL CLOCK DRIVER FOR SYNCH. DRAM & GEN. PURP. APPS W/SPREAD SPECTRUM COMPATIBILITY, POWER DOWN MODE 8-TSSOP -40 TO 85
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CDCVF2505PW
ActivePLL CLOCK DRIVER FOR SYNCH. DRAM & GEN. PURP. APPS W/SPREAD SPECTRUM COMPATIBILITY, POWER DOWN MODE 8-TSSOP -40 TO 85
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CDCVF2505PW | CDCVF2505 Series |
|---|---|---|
| Differential - Input:Output [custom] | False | False |
| Differential - Input:Output [custom] | False | False |
| Divider/Multiplier [custom] | False | False |
| Divider/Multiplier [custom] | False | False |
| Frequency - Max [Max] | 200 MHz | 200 MHz |
| Grade | - | Automotive |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Output | LVTTL | LVTTL |
| Package / Case | 8-TSSOP (0.173", 4.40mm Width) | 8-TSSOP (0.173", 4.40mm Width), 8-SOIC |
| Package / Case | - | 3.9 mm |
| PLL | Yes with Bypass | Yes with Bypass |
| Qualification | - | AEC-Q100 |
| Ratio - Input:Output [custom] | 1:5 | 1:5 |
| Supplier Device Package | 8-TSSOP | 8-TSSOP, 8-SOIC |
| Type | PLL Clock Driver | PLL Clock Driver |
| Voltage - Supply [Max] | 3.6 V | 3.6 V |
| Voltage - Supply [Min] | 3 V | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Chip1Stop | N/A | 1 | $ 1.61 | |
| 10 | $ 1.37 | |||
| DigiKey | N/A | 1 | $ 3.38 | |
| 10 | $ 2.54 | |||
| 25 | $ 2.33 | |||
| 150 | $ 2.05 | |||
| 157 | $ 1.91 | |||
| 300 | $ 1.97 | |||
| 600 | $ 1.91 | |||
| 1050 | $ 1.86 | |||
| 2550 | $ 1.81 | |||
| 5100 | $ 1.77 | |||
| Digikey | Tube | 1 | $ 2.49 | |
| 10 | $ 2.24 | |||
| 25 | $ 2.11 | |||
| 150 | $ 1.83 | |||
| 300 | $ 1.74 | |||
| 600 | $ 1.65 | |||
| Farnell | N/A | 1 | $ 5.84 | |
| 10 | $ 5.10 | |||
| 25 | $ 4.23 | |||
| 50 | $ 3.80 | |||
| 100 | $ 3.50 | |||
| 250 | $ 3.27 | |||
| 500 | $ 3.09 | |||
| Mouser Electronics | N/A | 1 | $ 3.38 | |
| 10 | $ 2.54 | |||
| 25 | $ 2.33 | |||
| 100 | $ 2.05 | |||
| 300 | $ 1.97 | |||
| 600 | $ 1.90 | |||
| 1050 | $ 1.80 | |||
| 3000 | $ 1.77 | |||
| Newark | N/A | 1 | $ 4.62 | |
| 10 | $ 4.35 | |||
| 25 | $ 4.12 | |||
| 50 | $ 3.93 | |||
| 100 | $ 3.76 | |||
| 300 | $ 3.58 | |||
| 600 | $ 3.52 | |||
| Quest Components | N/A | 1 | $ 4.50 | |
| 1 | $ 3.69 | |||
| 1 | $ 4.50 | |||
| 1 | $ 4.00 | |||
| 1 | $ 4.00 | |||
| 4 | $ 2.46 | |||
| 4 | $ 2.46 | |||
| 11 | $ 1.84 | |||
| 11 | $ 1.84 | |||
| 24 | $ 3.00 | |||
| 24 | $ 3.00 | |||
| 31 | $ 2.20 | |||
| 31 | $ 2.20 | |||
| 69 | $ 2.00 | |||
| 69 | $ 2.00 | |||
| 84 | $ 2.77 | |||
| 84 | $ 2.77 | |||
| Rochester Electronics | N/A | 1 | $ 1.84 | |
| 1 | $ 1.84 | |||
| 25 | $ 1.80 | |||
| 25 | $ 1.80 | |||
| 100 | $ 1.73 | |||
| 100 | $ 1.73 | |||
| 500 | $ 1.66 | |||
| 500 | $ 1.66 | |||
| 1000 | $ 1.56 | |||
| 1000 | $ 1.56 | |||
| Texas Instruments | TUBE | 1 | $ 2.75 | |
| 100 | $ 2.41 | |||
| 250 | $ 1.69 | |||
| 1000 | $ 1.36 | |||
| Verical | N/A | 174 | $ 2.16 | |
| 500 | $ 2.08 | |||
| 1000 | $ 1.95 | |||
| Win Source Electronics | N/A | 25 | $ 2.05 | |
| 60 | $ 1.68 | |||
| 93 | $ 1.63 | |||
| 127 | $ 1.58 | |||
| 165 | $ 1.52 | |||
| 220 | $ 1.37 | |||
CDCVF2505 Series
PLL clock driver for synch. DRAM & gen. purp. apps w/spread spectrum compatibility, power down mode
| Part | Output | Ratio - Input:Output [custom] | Package / Case | Supplier Device Package | Number of Circuits | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Divider/Multiplier [custom] | Divider/Multiplier [custom] | Mounting Type | Type | Operating Temperature [Min] | Operating Temperature [Max] | PLL | Voltage - Supply [Max] | Voltage - Supply [Min] | Frequency - Max [Max] | Package / Case | Grade | Qualification |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCVF2505PW | LVTTL | 1:5 | 8-TSSOP (0.173", 4.40mm Width) | 8-TSSOP | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | |||||||
Texas Instruments CDCVF2505DR | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505D | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505PWRG4 | LVTTL | 1:5 | 8-TSSOP (0.173", 4.40mm Width) | 8-TSSOP | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | |||||||
Texas Instruments CDCVF2505PWR | LVTTL | 1:5 | 8-TSSOP (0.173", 4.40mm Width) | 8-TSSOP | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | |||||||
Texas Instruments CDCVF2505DG4 | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505DRG4 | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505IDRQ1 | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | Automotive | AEC-Q100 |
Description
General part information
CDCVF2505 Series
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.
The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.
Documents
Technical documentation and resources