CDCVF2505 Series
PLL clock driver for synch. DRAM & gen. purp. apps w/spread spectrum compatibility, power down mode
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
PLL clock driver for synch. DRAM & gen. purp. apps w/spread spectrum compatibility, power down mode
| Part | Output | Ratio - Input:Output [custom] | Package / Case | Supplier Device Package | Number of Circuits | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Divider/Multiplier [custom] | Divider/Multiplier [custom] | Mounting Type | Type | Operating Temperature [Min] | Operating Temperature [Max] | PLL | Voltage - Supply [Max] | Voltage - Supply [Min] | Frequency - Max [Max] | Package / Case | Grade | Qualification |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCVF2505PW | LVTTL | 1:5 | 8-TSSOP (0.173", 4.40mm Width) | 8-TSSOP | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | |||||||
Texas Instruments CDCVF2505DR | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505D | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505PWRG4 | LVTTL | 1:5 | 8-TSSOP (0.173", 4.40mm Width) | 8-TSSOP | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | |||||||
Texas Instruments CDCVF2505PWR | LVTTL | 1:5 | 8-TSSOP (0.173", 4.40mm Width) | 8-TSSOP | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | |||||||
Texas Instruments CDCVF2505DG4 | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505DRG4 | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | ||||||
Texas Instruments CDCVF2505IDRQ1 | LVTTL | 1:5 | 8-SOIC | 8-SOIC | 1 | Surface Mount | PLL Clock Driver | -40 °C | 85 °C | Yes with Bypass | 3.6 V | 3 V | 200 MHz | 3.9 mm | Automotive | AEC-Q100 |
Key Features
• Phase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose ApplicationsSpread Spectrum Clock CompatibleOperating Frequency: 24 MHz to 200 MHzLow Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range)Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)Three-States Outputs When There Is No Input ClockOperates From Single 3.3-V SupplyAvailable in 8-Pin TSSOP and 8-Pin SOIC PackagesConsumes Less Than 100 mA (Typical) in Power-Down ModeInternal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock25-Ω On-Chip Series Damping ResistorsIntegrated RC PLL Loop Filter Eliminates the Need for External ComponentsPhase-Lock Loop Clock Driver for Synchronous DRAM and General-Purpose ApplicationsSpread Spectrum Clock CompatibleOperating Frequency: 24 MHz to 200 MHzLow Jitter (Cycle-to-Cycle): < |150 ps| (Over 66 MHz to 200 MHz Range)Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Used to Tune the Input-Output Delay)Three-States Outputs When There Is No Input ClockOperates From Single 3.3-V SupplyAvailable in 8-Pin TSSOP and 8-Pin SOIC PackagesConsumes Less Than 100 mA (Typical) in Power-Down ModeInternal Feedback Loop Is Used to Synchronize the Outputs to the Input Clock25-Ω On-Chip Series Damping ResistorsIntegrated RC PLL Loop Filter Eliminates the Need for External Components
Description
AI
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.
The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. This device uses a PLL to precisely align the output clocks (1Y[0-3] and CLKOUT) to the input clock signal (CLKIN) in both frequency and phase. The CDCVF2505 operates at 3.3 V and also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes into power-down mode when no input signal is applied to CLKIN.
The loop filter for the PLLs is included on-chip. This minimizes the component count, space, and cost.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.