Technical Specifications
Parameters and characteristics for this part
| Specification | EVALSTGAP2SICS |
|---|---|
| Contents | Board(s) |
| Function | Gate Driver |
| Supplied Contents | Board(s) |
| Type | Power Management |
| Utilized IC / Part | STGAP2SICS |
STGAP2SICSN Series
Galvanically isolated 4 A half-bridge dual channel gate driver
| Part | Package / Case | Package / Case [y] | Package / Case [x] | Voltage - Isolation | Approval Agency | Common Mode Transient Immunity (Min) [Min] | Mounting Type | Current - Output High, Low | Current - Output High, Low | Rise / Fall Time (Typ) [custom] | Rise / Fall Time (Typ) [custom] | Operating Temperature [Min] | Operating Temperature [Max] | Current - Peak Output | Pulse Width Distortion (Max) [Max] | Number of Channels | Supplier Device Package | Technology | Voltage - Output Supply [Max] | Voltage - Output Supply [Min] | Propagation Delay tpLH / tpHL (Max) [custom] | Propagation Delay tpLH / tpHL (Max) [custom] | Package / Case [custom] | Package / Case [custom] | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Utilized IC / Part | Contents | Function | Type | Supplied Contents | Number of Channels [custom] | Package / Case [custom] | Package / Case [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
STMicroelectronics | 8-SOIC | 3.9 mm | 0.154 in | 4000 Vrms | UL VDE | 100 V/ns | Surface Mount | 4 A | - | 30 ns | 30 ns | -40 °C | 125 ¯C | 4 A | 20 ns | 1 | 8-SO | Capacitive Coupling | 5.5 V | 3.1 V | 90 ns | 90 ns | ||||||||||||
STMicroelectronics | 8-SOIC | UL | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 °C | 4 A | 20 ns | 1 | 8-SO | Capacitive Coupling | 5.5 V | 3 V | 90 ns | 90 ns | 0.295 in | 7.5 mm | 4 A | 4 A | |||||||||||||
STMicroelectronics | 8-SOIC | 3.9 mm | 0.154 in | 1700 VDC | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 ¯C | 20 ns | 1 | 8-SO | Magnetic Coupling | 26 V | 9.6 V | 100 ns | 100 ns | 4 A | 4 A | ||||||||||||||
STMicroelectronics | 8-SOIC | 3.9 mm | 0.154 in | 4000 Vrms | UL | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 ¯C | 4 A | 20 ns | 1 | 8-SO | Capacitive Coupling | 26 V | 16.4 V | 90 ns | 90 ns | 4 A | 4 A | ||||||||||||
STMicroelectronics | 8-SOIC | UL | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 °C | 4 A | 20 ns | 1 | 8-SO | Capacitive Coupling | 5.5 V | 3 V | 90 ns | 90 ns | 0.295 in | 7.5 mm | 4 A | 4 A | |||||||||||||
STMicroelectronics | 8-SOIC | UL | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 °C | 4 A | 20 ns | 1 | 8-SO | Capacitive Coupling | 5.5 V | 3 V | 90 ns | 90 ns | 0.295 in | 7.5 mm | 4 A | 4 A | |||||||||||||
STMicroelectronics | STGAP2SICS | Board(s) | Gate Driver | Power Management | Board(s) | |||||||||||||||||||||||||||||
STMicroelectronics | 36-BSOP | 6000 Vrms | UL VDE | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 °C | 4 A | 36-SO | Capacitive Coupling | 5.5 V | 3.1 V | 90 ns | 90 ns | 7.5 mm | 4 A | 4 A | 2 | 32 | 0.295 in | ||||||||||||
STMicroelectronics | 8-SOIC | UL | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 °C | 4 A | 20 ns | 1 | 8-SO | Capacitive Coupling | 5.5 V | 3 V | 90 ns | 90 ns | 0.295 in | 7.5 mm | 4 A | 4 A | |||||||||||||
STMicroelectronics | 8-SOIC | 3.9 mm | 0.154 in | 1700 VDC | 100 V/ns | Surface Mount | 30 ns | 30 ns | -40 °C | 125 ¯C | 20 ns | 1 | 8-SO | Magnetic Coupling | 26 V | 9.6 V | 100 ns | 100 ns | 4 A | 4 A |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 1 | $ 59.24 | |
Description
General part information
STGAP2SICSN Series
The STGAP2SICSN is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry.
The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components.
The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shutdown are included to easily design high reliability systems. Dual input pins allow choosing the control signal polarity and also implementing HW interlocking protection in order to avoid cross-conduction in case of controller malfunction. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.
Documents
Technical documentation and resources