Technical Specifications
Parameters and characteristics for this part
| Specification | STGAP2SMTR |
|---|---|
| Common Mode Transient Immunity (Min) [Min] | 100 V/ns |
| Current - Output High, Low [custom] | 4 A |
| Current - Output High, Low [custom] | 4 A |
| Mounting Type | Surface Mount |
| Number of Channels | 1 |
| Operating Temperature [Max] | 125 ¯C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Propagation Delay tpLH / tpHL (Max) [custom] | 100 ns |
| Propagation Delay tpLH / tpHL (Max) [custom] | 100 ns |
| Pulse Width Distortion (Max) [Max] | 20 ns |
| Rise / Fall Time (Typ) [custom] | 30 ns |
| Rise / Fall Time (Typ) [custom] | 30 ns |
| Supplier Device Package | 8-SO |
| Technology | Magnetic Coupling |
| Voltage - Isolation | 1700 VDC |
| Voltage - Output Supply [Max] | 26 V |
| Voltage - Output Supply [Min] | 9.6 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.60 | |
| 10 | $ 1.43 | |||
| 25 | $ 1.35 | |||
| 100 | $ 1.15 | |||
| 250 | $ 1.08 | |||
| 500 | $ 0.95 | |||
| Digi-Reel® | 1 | $ 1.60 | ||
| 10 | $ 1.43 | |||
| 25 | $ 1.35 | |||
| 100 | $ 1.15 | |||
| 250 | $ 1.08 | |||
| 500 | $ 0.95 | |||
| Tape & Reel (TR) | 2500 | $ 0.95 | ||
| Newark | Each (Supplied on Cut Tape) | 1 | $ 2.21 | |
| 10 | $ 1.86 | |||
| 25 | $ 1.77 | |||
| 50 | $ 1.73 | |||
| 100 | $ 1.69 | |||
| 250 | $ 1.64 | |||
| 500 | $ 1.57 | |||
| 1000 | $ 1.56 | |||
Description
General part information
STGAP2SICSN Series
The STGAP2SICSN is a single gate driver which provides galvanic isolation between the gate driving channel and the low voltage control and interface circuitry.
The gate driver is characterized by 4 A capability and rail-to-rail outputs, making the device also suitable for mid and high power applications such as power conversion and motor driver inverters in industrial applications. The device is available in two different configurations. The configuration with separated output pins allows to independently optimize turn-on and turn-off by using dedicated gate resistors. The configuration featuring single output pin and Miller CLAMP function prevents gate spikes during fast commutations in half-bridge topologies. Both configurations provide high flexibility and bill of material reduction for external components.
The device integrates protection functions: UVLO with optimized value for SiC MOSFETs and thermal shutdown are included to easily design high reliability systems. Dual input pins allow choosing the control signal polarity and also implementing HW interlocking protection in order to avoid cross-conduction in case of controller malfunction. The input to output propagation delay results are contained within 75 ns, providing high PWM control accuracy. A standby mode is available in order to reduce idle power consumption.