ADC12DJ3200 Series
12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)
Manufacturer: Texas Instruments
Catalog(4 parts)
| Part | Voltage - Supply, Digital▲▼ | Voltage - Supply, Digital▲▼ | Number of Inputs▲▼ | Sampling Rate (Per Second)▲▼ | Number of A/D Converters▲▼ | Mounting Type | Input Type | Number of Bits▲▼ | Data Interface | Features | Configuration | Reference Type | Architecture | Operating Temperature▲▼ | Operating Temperature▲▼ | Ratio - S/H:ADC | Voltage - Supply, Analog▲▼ | Voltage - Supply, Analog▲▼ | Package / Case | Supplier Device Package | Supplied Contents | Utilized IC / Part | Contents |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1.149999976158142 V | 1.0499999523162842 V | 1 ul, 2 ul | 3200000000 Ω, 6400000000 Ω | 2 ul | Surface Mount | Differential, Single Ended | 12 ul | JESD204B | Simultaneous Sampling | MUX-ADC | Internal | Flash | -40 °C | 85 °C | 0:1 | 1.149999976158142 V, 2 V | 1.0499999523162842 V, 1.7999999523162842 V | ||||||
1.149999976158142 V | 1.0499999523162842 V | 1 ul, 2 ul | 3200000000 Ω, 6400000000 Ω | 2 ul | Surface Mount | Differential, Single Ended | 12 ul | JESD204B | Simultaneous Sampling | MUX-ADC | Internal | Flash | -40 °C | 85 °C | 0:1 | 1.149999976158142 V, 2 V | 1.0499999523162842 V, 1.7999999523162842 V | ||||||
Texas Instruments ADC12DJ3200AAV12 Bit Analog to Digital Converter 1, 2 Input 2 Flash 144-FCBGA (10x10) | 1.149999976158142 V | 1.0499999523162842 V | 1 ul, 2 ul | 3200000000 Ω | 2 ul | Surface Mount | Differential, Single Ended | 12 ul | JESD204B | Simultaneous Sampling | MUX-ADC | Internal | Flash | -40 °C | 85 °C | 0:1 | 1.149999976158142 V, 2 V | 1.0499999523162842 V, 1.7999999523162842 V | 144-FBGA, FCBGA | 144-FCBGA (10x10) | |||
Texas Instruments ADC12DJ3200EVMCVALADC12DJ3200QML-SP - 12 Bit 6.4G Samples per Second Analog to Digital Converter (ADC) Evaluation Board | 6400000000 Ω | 2 ul | 12 ul | JESD204B | Board(s) | ADC12DJ3200QML-SP | Board(s) |
Key Features
• ADC core:12-bit resolutionUp to 6.4 GSPS in single-channel modeUp to 3.2 GSPS in dual-channel modePerformance specifications:Noise floor (no signal, VFS= 1.0 VPP-DIFF):Dual-channel mode: –151.8 dBFS/HzSingle-channel mode: –154.6 dBFS/HzHD2, HD3: –65 dBc up to 3 GHzBuffered analog inputs with VCMIof 0 V:Analog input bandwidth (–3 dB): 8.0 GHzUsable input frequency range: >10 GHzFull-scale input voltage (VFS, default): 0.8 VPPAnalog input common-mode (VICM): 0 VNoiseless aperture delay (TAD) adjustment:Precise sampling control: 19-fs stepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingJESD204B serial data interface:Supports subclass 0 and 1Maximum lane rate: 12.8 GbpsUp to 16 lanes allows reduced lane rateDigital down-converters in dual-channel mode:Real output: DDC bypass or 2x decimationComplex output: 4x, 8x, or 16x decimationFour independent 32-Bit NCOs per DDCPower consumption: 3 WPower supplies: 1.1 V, 1.9 VADC core:12-bit resolutionUp to 6.4 GSPS in single-channel modeUp to 3.2 GSPS in dual-channel modePerformance specifications:Noise floor (no signal, VFS= 1.0 VPP-DIFF):Dual-channel mode: –151.8 dBFS/HzSingle-channel mode: –154.6 dBFS/HzHD2, HD3: –65 dBc up to 3 GHzBuffered analog inputs with VCMIof 0 V:Analog input bandwidth (–3 dB): 8.0 GHzUsable input frequency range: >10 GHzFull-scale input voltage (VFS, default): 0.8 VPPAnalog input common-mode (VICM): 0 VNoiseless aperture delay (TAD) adjustment:Precise sampling control: 19-fs stepSimplifies synchronization and interleavingTemperature and voltage invariant delaysEasy-to-use synchronization features:Automatic SYSREF timing calibrationTimestamp for sample markingJESD204B serial data interface:Supports subclass 0 and 1Maximum lane rate: 12.8 GbpsUp to 16 lanes allows reduced lane rateDigital down-converters in dual-channel mode:Real output: DDC bypass or 2x decimationComplex output: 4x, 8x, or 16x decimationFour independent 32-Bit NCOs per DDCPower consumption: 3 WPower supplies: 1.1 V, 1.9 V
Description
AI
The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).