Catalog(2 parts)
| Part | Function | Supplied Contents | Type | Contents | Utilized IC / Part | Embedded▲▼ | Supplier Device Package | Input | Package / Case | Voltage - Supply▲▼ | Voltage - Supply▲▼ | Frequency - Max▲▼ | Operating Temperature▲▼ | Operating Temperature▲▼ | Number of Circuits▲▼ | Differential - Input:Output▲▼ | Differential - Input:Output▲▼ | Mounting Type | Output | Ratio - Input:Output▲▼ | Ratio - Input:Output▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Clock Buffer | Board(s) | Timing | Board(s) | CDCLVD2102 | |||||||||||||||||
Texas Instruments CDCLVD2102RGTTClock Fanout Buffer (Distribution) IC 1:2 800 MHz 16-VFQFN Exposed Pad | Fanout Buffer (Distribution) | 16-VQFN (3x3) | LVCMOS, LVDS, LVPECL | 16-VFQFN Exposed Pad | 2.375 V | 2.625 V | 800000000 Hz | -40 °C | 85 °C | 2 ul | Surface Mount | LVDS | 1 ul | 2 ul |
Key Features
• Dual 1:2 Differential BufferLow Additive Jitter <300 fs RMS in 10-kHz to 20-MHzLow Within Bank Output Skew of 15 ps (Max)Universal Inputs Accept LVDS, LVPECL, LVCMOSOne Input Dedicated for Two OutputsTotal of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency up to 800 MHz2.375–2.625V Device Power SupplyLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range –40°C to 85°CPackaged in 3mm × 3mm 16-Pin QFN (RGT)ESD Protection Exceeds 3 kV HBM, 1 kV CDMAPPLICATIONSTelecommunications/NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose ClockingDual 1:2 Differential BufferLow Additive Jitter <300 fs RMS in 10-kHz to 20-MHzLow Within Bank Output Skew of 15 ps (Max)Universal Inputs Accept LVDS, LVPECL, LVCMOSOne Input Dedicated for Two OutputsTotal of 4 LVDS Outputs, ANSI EIA/TIA-644A Standard CompatibleClock Frequency up to 800 MHz2.375–2.625V Device Power SupplyLVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled InputsIndustrial Temperature Range –40°C to 85°CPackaged in 3mm × 3mm 16-Pin QFN (RGT)ESD Protection Exceeds 3 kV HBM, 1 kV CDMAPPLICATIONSTelecommunications/NetworkingMedical ImagingTest and Measurement EquipmentWireless CommunicationsGeneral Purpose Clocking
Description
AI
The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2102 is specifically designed for driving 50-transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package.
The CDCLVD2102 clock buffer distributes two clock inputs (IN0, IN1) to a total of 4 pairs of differential LVDS clock outputs (OUT0, OUT3). Each buffer block consists of one input and 2 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD2102 is specifically designed for driving 50-transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.
Using the control pin (EN), outputs can be either disabled or enabled. If the EN pin is left open two buffers with all outputs are enabled, if switched to a logical "0" both buffers with all outputs are disabled (static logical "0"), if switched to a logical "1", one buffer with two outputs is disabled and another buffer with two outputs is enabled. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.
The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2102 is packaged in small 16-pin, 3-mm × 3-mm QFN package.