The PI6CB332001A is a 20-output, very low-power, PCIe® 1.0/2.0/3.0/4.0/5.0/6.0 clock buffer. The device is capable of distributing the reference clocks for UPI, SAS, SATA, and other applications. It takes a reference input to fanout twenty 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save 80 external resistors and make layout easier. OE pins combined with SMBus bits, as well as a 3-wire side band interface, provide easier power management for each output. All OE pins are power down tolerant, which allows the OE pins to be driven by external signals when the device is in a power down or reset condition. The device must reset and power up properly if these pins are driven to any valid voltage prior to the assertion of VDD or PWRGD#.