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PI6CB332001A Series

20-Output PCIe 4.0/5.0/6.0 Clock Buffer With On-chip Termination

Manufacturer: Diodes Inc

Catalog

20-Output PCIe 4.0/5.0/6.0 Clock Buffer With On-chip Termination

Key Features

Supports Intel's DB2000QL Spec
3V Supply Voltage
HCSL Input: 100MHz (Typical), up to 400MHz
20 Differential Low-power HCSL Outputs with On-chip Termination
Two Output Enable Control ModesTraditional 8 OE# Pins with Power Down Tolerance and 20 SMBus bitsSimple 3-wire Side-Band Interface Real-time Control
Traditional 8 OE# Pins with Power Down Tolerance and 20 SMBus bits
Simple 3-wire Side-Band Interface Real-time Control
SMBus Interface Support
Spread Spectrum Tolerant
Very Low Jitter OutputsDifferential Additive Phase Jitter: DB2000Q <30fs RMSDifferential Additive Phase Jitter: PCIe 4.0 <30fs RMSDifferential Additive Phase Jitter: PCIe 5.0 <30fs RMSDifferential Additive Phase Jitter: PCIe 6.0 <16fs RMSPCIe 1.0/2.0/3.0/4.0/5.0/6.0 Compliant
Differential Additive Phase Jitter: DB2000Q <30fs RMS
Differential Additive Phase Jitter: PCIe 4.0 <30fs RMS
Differential Additive Phase Jitter: PCIe 5.0 <30fs RMS
Differential Additive Phase Jitter: PCIe 6.0 <16fs RMS
PCIe 1.0/2.0/3.0/4.0/5.0/6.0 Compliant
Differential Output-to-output Skew <50ps
Low Propagation Delay: <3ns
Industrial Temperature Support: -40°C to 85°C
Packaging (Pb-free & Green):80-lead 6x6mm dual-row aQFN
80-lead 6x6mm dual-row aQFN
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen- and Antimony-Free. "Green" Device (Note 3)
For automotive applications requiring specific change control (i.e. parts qualified to AEC-Q100/101/104/200, PPAP capable, and manufactured in IATF 16949 certified facilities), pleasecontact usor your local Diodes representative.https://www.diodes.com/quality/product-definitions/

Description

AI
The PI6CB332001A is a 20-output, very low-power, PCIe® 1.0/2.0/3.0/4.0/5.0/6.0 clock buffer. The device is capable of distributing the reference clocks for UPI, SAS, SATA, and other applications. It takes a reference input to fanout twenty 100MHz low-power differential HCSL outputs with on-chip terminations. The on-chip termination can save 80 external resistors and make layout easier. OE pins combined with SMBus bits, as well as a 3-wire side band interface, provide easier power management for each output. All OE pins are power down tolerant, which allows the OE pins to be driven by external signals when the device is in a power down or reset condition. The device must reset and power up properly if these pins are driven to any valid voltage prior to the assertion of VDD or PWRGD#.