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CD4072BE - 14-pin (N) package image

CD4072BE

Active
Texas Instruments

2-CH 4-INPUT 3-V TO 18-V OR GATE

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Search across all available documentation for this part.

DocumentsUnderstanding Buffered and Unbuffered CD4xxxB Series Device CharacteristicsSemiconductor Packing Material Electrostatic Discharge (ESD) Protection+5
CD4072BE - 14-pin (N) package image

CD4072BE

Active
Texas Instruments

2-CH 4-INPUT 3-V TO 18-V OR GATE

Deep-Dive with AI

DocumentsUnderstanding Buffered and Unbuffered CD4xxxB Series Device CharacteristicsSemiconductor Packing Material Electrostatic Discharge (ESD) Protection+5

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationCD4072BECD4072 Series
--
Current - Output High, Low3.4 mA, 3.4 mA3.4 mA
Current - Quiescent (Max) [Max]1 çA1 çA
Input Logic Level - High [Max]11 V11 V
Input Logic Level - High [Min]3.5 V3.5 V
Input Logic Level - Low [Max]4 V4 V
Input Logic Level - Low [Min]1.5 V1.5 V
Logic TypeOR GateOR Gate
Max Propagation Delay @ V, Max CL90 ns90 ns
Mounting TypeThrough HoleSurface Mount, Through Hole
Number of Circuits22
Number of Inputs44
Operating Temperature [Max]125 °C125 °C
Operating Temperature [Min]-55 °C-55 °C
Package / Case14-DIP14-SOIC, 14-TSSOP, 14-DIP
Package / Case7.62 mm3.9 - 7.62 mm
Package / Case0.3 in0.154 - 0.3 in
Package / Case-5.3 mm
Package / Case-0.209 in
Package / Case-0.173 in
Package / Case-4.4 mm
Supplier Device Package-14-SO, 14-TSSOP
Voltage - Supply [Max]18 V18 V
Voltage - Supply [Min]3 V3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.83
10$ 0.74
25$ 0.71
100$ 0.58
250$ 0.54
500$ 0.48
1000$ 0.38
2500$ 0.35
5000$ 0.34
Texas InstrumentsTUBE 1$ 0.72
100$ 0.49
250$ 0.38
1000$ 0.25

CD4072 Series

2-ch 4-input 3-V to 18-V OR gate

PartCurrent - Quiescent (Max) [Max]Number of CircuitsNumber of InputsInput Logic Level - High [Min]Input Logic Level - High [Max]Supplier Device PackageLogic TypeCurrent - Output High, LowMax Propagation Delay @ V, Max CLInput Logic Level - Low [Min]Input Logic Level - Low [Max]Mounting TypePackage / Case [y]Package / Case [y]Package / CaseOperating Temperature [Min]Operating Temperature [Max]Voltage - Supply [Max]Voltage - Supply [Min]Package / CasePackage / CasePackage / Case [custom]Package / Case [custom]
Texas Instruments
CD4072BNSR
1 çA
2
4
3.5 V
11 V
14-SO
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
5.3 mm
0.209 in
14-SOIC
-55 °C
125 °C
18 V
3 V
Texas Instruments
CD4072BM
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-SOIC
-55 °C
125 °C
18 V
3 V
3.9 mm
0.154 in
Texas Instruments
CD4072BNS
Texas Instruments
CD4072BPW
1 çA
2
4
3.5 V
11 V
14-TSSOP
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-TSSOP
-55 °C
125 °C
18 V
3 V
0.173 in
4.4 mm
Texas Instruments
CD4072BMT
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-SOIC
-55 °C
125 °C
18 V
3 V
3.9 mm
0.154 in
Texas Instruments
CD4072BPWG4
1 çA
2
4
3.5 V
11 V
14-TSSOP
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-TSSOP
-55 °C
125 °C
18 V
3 V
0.173 in
4.4 mm
Texas Instruments
CD4072BM96
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-SOIC
-55 °C
125 °C
18 V
3 V
3.9 mm
0.154 in
Texas Instruments
CD4072BE
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Through Hole
14-DIP
-55 °C
125 °C
18 V
3 V
7.62 mm
0.3 in

Description

General part information

CD4072 Series

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.

The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates.