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CD4072 Series

2-ch 4-input 3-V to 18-V OR gate

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

2-ch 4-input 3-V to 18-V OR gate

PartCurrent - Quiescent (Max) [Max]Number of CircuitsNumber of InputsInput Logic Level - High [Min]Input Logic Level - High [Max]Supplier Device PackageLogic TypeCurrent - Output High, LowMax Propagation Delay @ V, Max CLInput Logic Level - Low [Min]Input Logic Level - Low [Max]Mounting TypePackage / Case [y]Package / Case [y]Package / CaseOperating Temperature [Min]Operating Temperature [Max]Voltage - Supply [Max]Voltage - Supply [Min]Package / CasePackage / CasePackage / Case [custom]Package / Case [custom]
Texas Instruments
CD4072BNSR
1 çA
2
4
3.5 V
11 V
14-SO
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
5.3 mm
0.209 in
14-SOIC
-55 °C
125 °C
18 V
3 V
Texas Instruments
CD4072BM
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-SOIC
-55 °C
125 °C
18 V
3 V
3.9 mm
0.154 in
Texas Instruments
CD4072BNS
Texas Instruments
CD4072BPW
1 çA
2
4
3.5 V
11 V
14-TSSOP
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-TSSOP
-55 °C
125 °C
18 V
3 V
0.173 in
4.4 mm
Texas Instruments
CD4072BMT
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-SOIC
-55 °C
125 °C
18 V
3 V
3.9 mm
0.154 in
Texas Instruments
CD4072BPWG4
1 çA
2
4
3.5 V
11 V
14-TSSOP
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-TSSOP
-55 °C
125 °C
18 V
3 V
0.173 in
4.4 mm
Texas Instruments
CD4072BM96
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Surface Mount
14-SOIC
-55 °C
125 °C
18 V
3 V
3.9 mm
0.154 in
Texas Instruments
CD4072BE
1 çA
2
4
3.5 V
11 V
OR Gate
3.4 mA, 3.4 mA
90 ns
1.5 V
4 V
Through Hole
14-DIP
-55 °C
125 °C
18 V
3 V
7.62 mm
0.3 in

Key Features

• Medium-Speed Operation - tPLH, tPHL= 60 ns (typ.) at VDD= 10 V100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CStandardized, symmetrical output characteristicsNoise margin (full package-temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Data sheet acquired from Harris SemiconductorMedium-Speed Operation - tPLH, tPHL= 60 ns (typ.) at VDD= 10 V100% tested for quiescent current at 20 VMaximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°CStandardized, symmetrical output characteristicsNoise margin (full package-temperature range):1 V at VDD= 5 V2 V at VDD= 10 V2.5 V at VDD= 15 V5-V, 10-V, and 15-V parametric ratingsMeets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"Data sheet acquired from Harris Semiconductor

Description

AI
CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes). CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR function and supplement the existing family of CMOS gates. The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-lead thin shrink small-outline packages (PW and PWR suffixes).