
CD74HC174M96
ActiveTexas Instruments
HIGH SPEED CMOS LOGIC HEX D-TYPE FLIP-FLOPS WITH RESET

CD74HC174M96
ActiveTexas Instruments
HIGH SPEED CMOS LOGIC HEX D-TYPE FLIP-FLOPS WITH RESET
Description
General part information
74HC174 Series
The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.
The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.
Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HC174M96 |
|---|---|
| Clock Frequency | 35 MHz |
| Current - Output High | 5.2 mA |
| Current - Output Low | 5.2 mA |
| Current - Quiescent (Iq) | 8 µA |
| Function | Master Reset |
| Input Capacitance | 10 pF |
| Max CL | 50 pF |
| Max Propagation Delay | 28 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 6 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 125 °C |
| Operating Temperature (Min) | -55 °C |
| Output Type | Non-Inverted |
| Package Length | 0.154 in |
| Package Name | 16-SOIC |
| Package Width | 3.9 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply (Maximum) | 6 V |
| Voltage - Supply (Minimum) | 2 V |
Pricing
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CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Power-Up Behavior of Clocked Devices (Rev. B)
LOGIC Pocket Data Book (Rev. B)
Input and Output Characteristics of Digital Integrated Circuits
Logic Guide (Rev. AB)
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 datasheet (Rev. C)
Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
Signal Switch Data Book (Rev. A)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Live Insertion
CMOS Power Consumption and CPD Calculation (Rev. B)
TI IBIS File Creation, Validation, and Distribution Processes
Designing With Logic (Rev. C)
Implications of Slow or Floating CMOS Inputs (Rev. E)
SN54/74HCT CMOS Logic Family Applications and Restrictions