
SN74AHCT174DBR
ActiveTexas Instruments
HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN74AHCT174DBR
ActiveTexas Instruments
HEX D-TYPE FLIP-FLOPS WITH CLEAR
Description
General part information
74AHCT174 Series
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHCT174DBR |
|---|---|
| Clock Frequency | 115 MHz |
| Current - Output High | 8 mA |
| Current - Output Low | 8 mA |
| Current - Quiescent (Iq) | 4 µA |
| Function | Master Reset |
| Input Capacitance | 2 pF |
| Max CL | 50 pF |
| Max Propagation Delay | 8.8 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 6 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output Type | Non-Inverted |
| Package Length | 0.209 in |
| Package Name | 16-SSOP |
| Package Width | 5.3 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply (Maximum) | 5.5 V |
| Voltage - Supply (Minimum) | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Sign in to see pricing
Create a free account to access distributor pricing data.
CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
CMOS Power Consumption and CPD Calculation (Rev. B)
Power-Up Behavior of Clocked Devices (Rev. B)
Implications of Slow or Floating CMOS Inputs (Rev. E)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
AHC/AHCT Designer's Guide February 2000 (Rev. D)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Logic Guide (Rev. AB)
How to Select Little Logic (Rev. A)
SN74AHCT174 Hex D-Type Flip-Flops with Clear datasheet (Rev. H)
Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)
TI IBIS File Creation, Validation, and Distribution Processes
Live Insertion
Little Logic Guide 2018 (Rev. G)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Selecting the Right Level Translation Solution (Rev. A)
Texas Instruments Little Logic Application Report
LOGIC Pocket Data Book (Rev. B)
Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)
Design Summary for WCSP Little Logic (Rev. B)