SN74AHCT174DR
ActiveTexas Instruments
FLIP FLOPS HEX D-TYPE FLIP-FLOP WITH CLEAR A 595-SN74AHCT174D
SN74AHCT174DR
ActiveTexas Instruments
FLIP FLOPS HEX D-TYPE FLIP-FLOP WITH CLEAR A 595-SN74AHCT174D
Description
General part information
74AHCT174 Series
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.
These positive-edge-triggered D-type flip-flops have a direct clear (CLR) input.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHCT174DR |
|---|---|
| Clock Frequency | 115 MHz |
| Current - Output High | 8 mA |
| Current - Output Low | 8 mA |
| Current - Quiescent (Iq) | 4 µA |
| Function | Master Reset |
| Input Capacitance | 2 pF |
| Max CL | 50 pF |
| Max Propagation Delay | 8.8 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 6 bits |
| Number of Elements | 1 |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output Type | Non-Inverted |
| Package Length | 0.154 in |
| Package Name | 16-SOIC |
| Package Width | 3.9 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply (Maximum) | 5.5 V |
| Voltage - Supply (Minimum) | 4.5 V |
Pricing
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CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
AHC/AHCT Designer's Guide February 2000 (Rev. D)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
LOGIC Pocket Data Book (Rev. B)
Live Insertion
Little Logic Guide 2018 (Rev. G)
Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)
CMOS Power Consumption and CPD Calculation (Rev. B)
How to Select Little Logic (Rev. A)
Implications of Slow or Floating CMOS Inputs (Rev. E)
Texas Instruments Little Logic Application Report
Logic Guide (Rev. AB)
SN74AHCT174 Hex D-Type Flip-Flops with Clear datasheet (Rev. H)
Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)
Selecting the Right Level Translation Solution (Rev. A)
Power-Up Behavior of Clocked Devices (Rev. B)
Design Summary for WCSP Little Logic (Rev. B)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
TI IBIS File Creation, Validation, and Distribution Processes
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
