Zenode.ai Logo
SN74LVC1G175DCKR

SN74LVC1G175DCKR

Active
Texas Instruments

SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR

Find alt
SN74LVC1G175DCKR

SN74LVC1G175DCKR

Active
Texas Instruments

SINGLE D-TYPE FLIP-FLOP WITH ASYNCHRONOUS CLEAR

Find alt

Description

General part information

SN74LVC1G175 Series

This single D-type flip-flop is designed for 1.65-V to 5.5-V VCCoperation.

The SN74LVC1G175 device has an asynchronous clear (CLR) input. WhenCLRis high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. WhenCLRis low, Q is forced into the low state, regardless of the clock edge or data on D.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74LVC1G175DCKR
Clock Frequency175 MHz
Current - Output High32 mA
Current - Output Low32 mA
Current - Quiescent (Iq)10 µA
FunctionReset
Input Capacitance3 pF
Max CL50 pF
Max Propagation Delay5 ns
Mounting TypeSurface Mount
Number of Bits per Element1 bits
Number of Elements1
Operating Temperature (Max)125 °C
Operating Temperature (Min)-40 °C
Output TypeNon-Inverted
Package / Case6-TSSOP, SC-88, SOT-363
Package NameSC-70-6
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply (Maximum)5.5 V
Voltage - Supply (Minimum)1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Sign in to see pricing

Create a free account to access distributor pricing data.

Sign up — freeLog in

CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

SN74LVC1G175DCKR | Datasheet
Live Insertion
Generate an Enable Signal that can be Toggled
Understanding Advanced Bus-Interface Products Design Guide
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
CMOS Power Consumption and CPD Calculation (Rev. B)
Implications of Slow or Floating CMOS Inputs (Rev. E)
Logic Guide (Rev. AB)
SN74LVC1G175 Single D-Type Flip-Flop With Asynchronous Clear datasheet (Rev. G)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Texas Instruments Little Logic Application Report
Power-Up Behavior of Clocked Devices (Rev. B)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Low-Voltage Logic (LVC) Designer's Guide
Little Logic Guide 2018 (Rev. G)
Design Summary for WCSP Little Logic (Rev. B)
How to Select Little Logic (Rev. A)
Selecting the Right Level Translation Solution (Rev. A)
Signal Switch Data Book (Rev. A)
Use of the CMOS Unbuffered Inverter in Oscillator Circuits
Standard Linear & Logic for PCs, Servers & Motherboards
TI IBIS File Creation, Validation, and Distribution Processes
LOGIC Pocket Data Book (Rev. B)
LVC Characterization Information
Push-Button Circuit (Rev. B)
Input and Output Characteristics of Digital Integrated Circuits