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1517-FCBGA

66AK2H12DXAAWA24

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Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 8X C66X DSP CORES

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1517-FCBGA

66AK2H12DXAAWA24

Active
Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 8X C66X DSP CORES

Find alt

Description

General part information

66AK2H12 Series

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows®debugger interface for visibility into source code execution.

Technical Specifications

Parameters and characteristics for this part

Specification66AK2H12DXAAWA24
Clock Rate (ARM®)1.4 GHz
Clock Rate (Core Types)DSP, ARM®
Clock Rate (DSP)1.2 GHz
InterfaceUART/USART, Serial RapidIO, USB, DMA, EBI/EMI, I2C, SPI, Ethernet
Mounting TypeSurface Mount
Non-Volatile Memory Size384 kB
Non-Volatile Memory TypeROM
On-Chip RAM12.75 MB
Operating Temperature (Max)100 °C
Operating Temperature (Min)-40 °C
Package / Case1517-BBGA, FCBGA
Package Length40 mm
Package Name1517-FCBGA
Package Width40 mm
TypeDSP+ARM®
USB Version3
Voltage - CoreVariable
Voltage - I/O (Option 1)0.85 V
Voltage - I/O (Option 2)1 V
Voltage - I/O (Option 3)1.35 V
Voltage - I/O (Option 4)1.5 V
Voltage - I/O (Option 5)1.8 V
Voltage - I/O (Option 6)3.3 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

66AK2H12DXAAWA24 | Datasheet
General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide
KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A)
Keystone Multicore Device Family Schematic Checklist
ARM Assembly Language Tools v5.2 User's Guide (Rev. M)
Multicore Programming Guide (Rev. B)
Video Infrastructure - Applications of the K2E, K2H platforms
Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)
External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)
Hardware Design Guide for KeyStone II Devices
C66x CPU and Instruction Set Reference Guide
Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)
Clocking Design Guide for KeyStone Devices
Introduction to TMS320C6000 DSP Optimization
TI’s processors leading the way in embedded analytics
Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)
66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F)
ARM Bootloader User Guide for KeyStone II Devices
Keystone II DDR3 Debug Guide
Keystone Error Detection and Correction EDC ECC (Rev. A)
Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)
PCIe Use Cases for KeyStone Devices
66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A)
Thermal Design Guide for DSP and Arm Application Processors (Rev. B)
Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide
PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)
Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)
Keystone NDK FAQ
Throughput Performance Guide for KeyStone II Devices (Rev. B)
SERDES Link Commissioning on KeyStone I and II Devices
TI DSP Benchmarking
Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B)
Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices
Power Consumption Summary for 66AK2Hx System-on-Chip (SoC) Device Family
Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)
Software and Hardware Design Challenges Due to Dynamic Raw NAND Market
Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)
Multicore DSPs for High-Performance Video Coding
KeyStone™-II-based processors: 10G Ethernet as an optical interface
Using DSPLIB FFT Implementation for Real Input and Without Data Scaling
Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG
Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)
66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G)
HyperLink for KeyStone Devices User's Guide (Rev. C)
DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)
64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)
Industrial Imaging: Applications of the K2H and K2E platforms
C66x CorePac User's Guide (Rev. C)
Power Management of KS2 Device (Rev. C)
DDR3 Design Requirements for KeyStone Devices (Rev. D)
Optimizing Loops on the C66x DSP
Debug and Trace for KeyStone II Devices User's Guide
Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)
Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)
Implementing an FTP Server on TI 66AK2H Device With RTOS
Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D)
Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)
Using Arm ROM Bootloader on Keystone II Devices
C66x DSP Cache User's Guide
ARM CorePac User Guide for KeyStone II Devices
Network Coprocessor for KeyStone Devices User's Guide
KeyStone II DDR3 interface bring-up
DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)
ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J)
Keystone EDMA FAQ
Keystone II DDR3 Initialization
How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)
Multicore SoCs stay a step ahead of SoC FPGAs