CD74ACT109M
ActiveDUAL POSITIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
Deep-Dive with AI
Search across all available documentation for this part.
CD74ACT109M
ActiveDUAL POSITIVE-EDGE TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
Deep-Dive with AI
Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CD74ACT109M | 74ACT109 Series |
|---|---|---|
| Clock Frequency | 100 MHz | 100 MHz |
| Current - Output High, Low [custom] | 24 mA | 24 mA |
| Current - Output High, Low [custom] | 24 mA | 24 mA |
| Current - Quiescent (Iq) | 4 çA | 4 çA |
| Function | Reset, Set(Preset) | Reset, Set(Preset) |
| Input Capacitance | 10 pF | 10 pF |
| Max Propagation Delay @ V, Max CL | 10.3 ns | 10.3 ns |
| Mounting Type | Surface Mount | Through Hole, Surface Mount |
| Number of Bits per Element | 1 | 1 |
| Number of Elements [custom] | 2 | 2 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 C | -55 C |
| Output Type | Complementary | Complementary |
| Package / Case | 16-SOIC | 16-DIP, 16-SOIC |
| Package / Case | 3.9 mm Width, 0.154 in | 0.154 - 7.62 in |
| Supplier Device Package | 16-SOIC | 16-PDIP, 16-SOIC |
| Trigger Type | Positive Edge | Positive Edge |
| Type | JK Type | JK Type |
| Voltage - Supply [Max] | 5.5 V | 5.5 V |
| Voltage - Supply [Min] | 4.5 V | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
74ACT109 Series
IC FF JK TYPE DUAL 1BIT 16DIP
| Part | Number of Bits per Element | Supplier Device Package | Clock Frequency | Trigger Type | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Output Type | Max Propagation Delay @ V, Max CL | Operating Temperature [Min] | Operating Temperature [Max] | Current - Quiescent (Iq) | Mounting Type | Number of Elements [custom] | Voltage - Supply [Max] | Voltage - Supply [Min] | Function | Type | Input Capacitance | Package / Case | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74ACT109EG4Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-DIP (0.300", 7.62mm) | 1 | 16-PDIP | 100 MHz | Positive Edge | 24 mA | 24 mA | Complementary | 10.3 ns | -55 C | 125 °C | 4 çA | Through Hole | 2 | 5.5 V | 4.5 V | Reset, Set(Preset) | JK Type | 10 pF | 0.3 in, 7.62 mm | 16-DIP |
Texas Instruments CD74ACT109ME4Flip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width) | 1 | 16-SOIC | 100 MHz | Positive Edge | 24 mA | 24 mA | Complementary | 10.3 ns | -55 C | 125 °C | 4 çA | Surface Mount | 2 | 5.5 V | 4.5 V | Reset, Set(Preset) | JK Type | 10 pF | 0.154 in, 3.9 mm Width | 16-SOIC |
Texas Instruments CD74ACT109EThe ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. | 1 | 16-PDIP | 100 MHz | Positive Edge | 24 mA | 24 mA | Complementary | 10.3 ns | -55 C | 125 °C | 4 çA | Through Hole | 2 | 5.5 V | 4.5 V | Reset, Set(Preset) | JK Type | 10 pF | 0.3 in, 7.62 mm | 16-DIP |
Texas Instruments CD74ACT109MThe ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. | 1 | 16-SOIC | 100 MHz | Positive Edge | 24 mA | 24 mA | Complementary | 10.3 ns | -55 C | 125 °C | 4 çA | Surface Mount | 2 | 5.5 V | 4.5 V | Reset, Set(Preset) | JK Type | 10 pF | 0.154 in, 3.9 mm Width | 16-SOIC |
Texas Instruments CD74ACT109M96The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together. | 1 | 16-SOIC | 100 MHz | Positive Edge | 24 mA | 24 mA | Complementary | 10.3 ns | -55 C | 125 °C | 4 çA | Surface Mount | 2 | 5.5 V | 4.5 V | Reset, Set(Preset) | JK Type | 10 pF | 0.154 in, 3.9 mm Width | 16-SOIC |
Description
General part information
74ACT109 Series
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
The ’ACT109 devices contain two independent J-K\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\ or clear (CLR)\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the J and K\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\ and tying J high. They also can perform as D-type flip-flops if J and K\ are tied together.
Documents
Technical documentation and resources