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CDCLVD1213EVM - CDCLVD1213EVM

CDCLVD1213EVM

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Texas Instruments

EVAL MODULE FOR CDCLVD1213

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CDCLVD1213EVM - CDCLVD1213EVM

CDCLVD1213EVM

Active
Texas Instruments

EVAL MODULE FOR CDCLVD1213

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationCDCLVD1213EVMCDCLVD1213 Series
Differential - Input:Output-True
Differential - Input:Output-True
EmbeddedFalseFalse
Frequency - Max-800 MHz
FunctionClock BufferClock Buffer
Mounting Type-Surface Mount
Number of Circuits-1
Operating Temperature--40 °C
Operating Temperature-85 °C
Output-LVDS
Package / Case-16-VFQFN Exposed Pad
Ratio - Input:Output-4
Ratio - Input:Output-1
Supplied ContentsBoard(s)Board(s)
Supplier Device Package-16-VQFN (3x3)
TypeTimingFanout Buffer (Distribution), Divider, Timing
Utilized IC / PartCDCLVD1213CDCLVD1213
Voltage - Supply-2.375 V
Voltage - Supply-2.625 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBox 1$ 178.80

CDCLVD1213 Series

Low jitter, 1:4 universal-to-LVDS buffer with selectable output divider

PartSupplier Device PackageOutputDifferential - Input:Output [custom]Differential - Input:Output [custom]Operating Temperature [Min]Operating Temperature [Max]Voltage - Supply [Min]Voltage - Supply [Max]TypePackage / CaseFrequency - Max [Max]Ratio - Input:Output [custom]Ratio - Input:Output [custom]Number of CircuitsMounting TypeSupplied ContentsUtilized IC / PartFunctionEmbedded
Texas Instruments
CDCLVD1213RGTR
16-VQFN (3x3)
LVDS
-40 °C
85 °C
2.375 V
2.625 V
Fanout Buffer (Distribution), Divider
16-VFQFN Exposed Pad
800 MHz
4
1
1
Surface Mount
Texas Instruments
CDCLVD1213RGTT
16-VQFN (3x3)
LVDS
-40 °C
85 °C
2.375 V
2.625 V
Fanout Buffer (Distribution), Divider
16-VFQFN Exposed Pad
800 MHz
4
1
1
Surface Mount
Texas Instruments
CDCLVD1213EVM
Timing
Board(s)
CDCLVD1213
Clock Buffer

Description

General part information

CDCLVD1213 Series

The CDCLVD1213 clock buffer distributes an input clock to 4 pairs of differential LVDS clock outputs with low additive jitter for clock distribution. The input can either be LVDS, LVPECL, or CML.

The CDCLVD1213 contains a high performance divider for one output (QD) which can divide the input clock signal by a factor of 1, 2, or 4.

The CDCLVD1213 is specifically designed for driving 50-Ω transmission lines. The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

Documents

Technical documentation and resources