JM38510/37201BEA
ActiveTexas Instruments
HEX D-TYPE FLIP-FLOPS WITH CLEAR 16-CDIP -55 TO 125
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JM38510/37201BEA
ActiveTexas Instruments
HEX D-TYPE FLIP-FLOPS WITH CLEAR 16-CDIP -55 TO 125
Deep-Dive with AI
Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | JM38510/37201BEA | SN54ALS174 Series |
|---|---|---|
| Clock Frequency | 40 MHz | 40 MHz |
| Current - Output High, Low [custom] | 400 µA | 400 µA |
| Current - Output High, Low [custom] | 4 mA | 4 mA |
| Current - Quiescent (Iq) | 19 mA | 19 mA |
| Grade | Military | Military |
| Max Propagation Delay @ V, Max CL | 24 ns | 24 ns |
| Mounting Type | Through Hole | Through Hole, Surface Mount |
| Number of Bits per Element | 6 | 6 |
| Number of Elements [custom] | 1 | 1 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 C | -55 C |
| Output Type | Non-Inverted | Non-Inverted |
| Package / Case | 16-CDIP (0.300", 7.62mm) | 16-CDIP (0.300", 7.62mm), 20-CLCC |
| Qualification | MIL-PRF-38535L | MIL-PRF-38535L |
| Supplier Device Package | 16-CDIP | 16-CDIP, 20-LCCC |
| Supplier Device Package | - | 8.89 |
| Supplier Device Package | - | 8.89 |
| Trigger Type | Positive Edge | Positive Edge |
| Type | D-Type | D-Type |
| Voltage - Supply [Max] | 5.5 V | 5.5 V |
| Voltage - Supply [Min] | 4.5 V | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
SN54ALS174 Series
Hex D-type Flip-Flops With Clear
| Part | Supplier Device Package | Output Type | Voltage - Supply [Max] | Voltage - Supply [Min] | Number of Bits per Element | Mounting Type | Current - Quiescent (Iq) | Type | Clock Frequency | Max Propagation Delay @ V, Max CL | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Operating Temperature [Min] | Operating Temperature [Max] | Package / Case | Number of Elements [custom] | Trigger Type | Grade | Qualification | Supplier Device Package [y] | Supplier Device Package [x] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments SNJ54ALS174JThese positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits. | 16-CDIP | Non-Inverted | 5.5 V | 4.5 V | 6 | Through Hole | 19 mA | D-Type | 40 MHz | 24 ns | 400 µA | 4 mA | -55 C | 125 °C | 16-CDIP (0.300", 7.62mm) | 1 | Positive Edge | ||||
Texas Instruments JM38510/37201BEAThese positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits. | 16-CDIP | Non-Inverted | 5.5 V | 4.5 V | 6 | Through Hole | 19 mA | D-Type | 40 MHz | 24 ns | 400 µA | 4 mA | -55 C | 125 °C | 16-CDIP (0.300", 7.62mm) | 1 | Positive Edge | Military | MIL-PRF-38535L | ||
Texas Instruments M38510/37201B2AThese positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits. | 20-LCCC | Non-Inverted | 5.5 V | 4.5 V | 6 | Surface Mount | 19 mA | D-Type | 40 MHz | 24 ns | 400 µA | 4 mA | -55 C | 125 °C | 20-CLCC | 1 | Positive Edge | 8.89 | 8.89 | ||
Texas Instruments SN54ALS174JThese positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits. | 16-CDIP | Non-Inverted | 5.5 V | 4.5 V | 6 | Through Hole | 19 mA | D-Type | 40 MHz | 24 ns | 400 µA | 4 mA | -55 C | 125 °C | 16-CDIP (0.300", 7.62mm) | 1 | Positive Edge |
Description
General part information
SN54ALS174 Series
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
These circuits are fully compatible for use with most TTL circuits.
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Technical documentation and resources