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SN54ALS174 Series

Hex D-type Flip-Flops With Clear

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

Hex D-type Flip-Flops With Clear

PartSupplier Device PackageOutput TypeVoltage - Supply [Max]Voltage - Supply [Min]Number of Bits per ElementMounting TypeCurrent - Quiescent (Iq)TypeClock FrequencyMax Propagation Delay @ V, Max CLCurrent - Output High, Low [custom]Current - Output High, Low [custom]Operating Temperature [Min]Operating Temperature [Max]Package / CaseNumber of Elements [custom]Trigger TypeGradeQualificationSupplier Device Package [y]Supplier Device Package [x]
Texas Instruments
SNJ54ALS174J
16-CDIP
Non-Inverted
5.5 V
4.5 V
6
Through Hole
19 mA
D-Type
40 MHz
24 ns
400 µA
4 mA
-55 C
125 °C
16-CDIP (0.300", 7.62mm)
1
Positive Edge
Texas Instruments
JM38510/37201BEA
16-CDIP
Non-Inverted
5.5 V
4.5 V
6
Through Hole
19 mA
D-Type
40 MHz
24 ns
400 µA
4 mA
-55 C
125 °C
16-CDIP (0.300", 7.62mm)
1
Positive Edge
Military
MIL-PRF-38535L
Texas Instruments
M38510/37201B2A
20-LCCC
Non-Inverted
5.5 V
4.5 V
6
Surface Mount
19 mA
D-Type
40 MHz
24 ns
400 µA
4 mA
-55 C
125 °C
20-CLCC
1
Positive Edge
8.89
8.89
Texas Instruments
SN54ALS174J
16-CDIP
Non-Inverted
5.5 V
4.5 V
6
Through Hole
19 mA
D-Type
40 MHz
24 ns
400 µA
4 mA
-55 C
125 °C
16-CDIP (0.300", 7.62mm)
1
Positive Edge

Key Features

’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)’ALS174 and ’AS174 Contain Six Flip-Flops With Single-Rail Outputs’ALS175 and ’AS175B Contain Four Flip-Flops With Double-Rail OutputsBuffered Clock and Direct-Clear InputsApplications Include:Buffer/Storage RegistersShift RegistersPattern GeneratorsFully Buffered Outputs for Maximum Isolation From External Disturbances (’AS Only)

Description

AI
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits. These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct-clear (CLR)\ input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop. Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. These circuits are fully compatible for use with most TTL circuits.