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TPS621361RGXT

TPS621361RGXT

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Texas Instruments

3-17V 4.0A STEP-DOWN CONVERTER WITH 1% ACCURACY AND PFM/FORCED-PWM IN 2X3QFN

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TPS621361RGXT

TPS621361RGXT

Active
Texas Instruments

3-17V 4.0A STEP-DOWN CONVERTER WITH 1% ACCURACY AND PFM/FORCED-PWM IN 2X3QFN

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Description

General part information

TPS62136 Series

The TPS62136 and TPS621361 are high efficiency and easy to use synchronous step-down DC-DC converters, based on the DCS-Control™ Topology. The devices wide input voltage range of 3-V to 17-V makes it suitable for multi-cell Li-Ion as well as 12-V intermediate supply rails. The devices provide 4-A continuous output current. The TPS62136 automatically enters Power Save Mode at light loads to maintain high efficiency across the whole load range. With that, the device is well suited for applications that require connected standby performance, like ultra low power computers. With the MODE pin set to low, the switching frequency of the device is adapted automatically based on the input and output voltage. This technique is called Automatic Efficiency Enhancement (AEE™) and maintains high conversion efficiency over the whole operation range. It provides a 1% output voltage accuracy in PWM mode and therefore enables the design of a power supply with high output voltage accuracy.

The device has a typical quiescent current of 18 µA. In shutdown mode the current is typically 1 µA and the output is actively discharged for TPS62136 while the output voltage discharge feature is disabled in TPS621361.

The TPS62136 is available as an adjustable version, packaged in a 3-mm x 2-mm VQFN package.

Technical Specifications

Parameters and characteristics for this part

SpecificationTPS621361RGXT
Current - Output4 A
Frequency - Switching1 MHz
FunctionStep-Down
Mounting TypeSurface Mount
Number of Outputs1
Operating Temperature (Max)125 °C
Operating Temperature (Min)-40 °C
Output ConfigurationPositive
Output TypeAdjustable
Package / Case11-VFQFN
Package Length2 mm
Package Name11-VQFN-HR
Package Width3 mm
Synchronous RectifierYes
TopologyBuck
Voltage - Input (Max)17 V
Voltage - Input (Min)3 V
Voltage - Output (Max)12 V
Voltage - Output (Min/Fixed)0.8 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

QFN and SON PCB Attachment (Rev. C)
Output accuracy varies with temperature – 1% is not always 1%
High-efficiency, low-ripple DCS-Control offers seamless PWM/pwr-save transitions
Sequencing and Tracking With the TPS621-Family and TPS821-Family (Rev. A)
Performing Accurate PFM Mode Efficiency Measurements (Rev. A)
Five steps to a great PCB layout for a step-down converter
Step-Down LED Driver With Dimming With the TPS621-Family and TPS821-Family (Rev. A)
How to modify a step-down converter to the inverting buck-boost topology
Voltage Margining Using the TPS62130
TPS6213xEVM Buck Converter Evaluation Module User's Guide (Rev. B)
IQ: What it is, what it isn’t, and how to use it
Using the TPS62150 in a Split Rail Topology
Feedforward Capacitor to Improve Stability and Bandwidth of TPS621/821-Family (Rev. A)
Quick Reference Guide To TI Buck Switching DC/DC Application Notes (Rev. B)
Minimize the impact of the MLCC shortage on your power application
Basic Calculation of a Buck Converter's Power Stage (Rev. B)
TPS62136, TPS621361 1-MHz High Accuracy 3-V to 17-V 4-A Step-Down Converters with DCS ControlTM datasheet
Understanding the Absolute Maximum Ratings of the SW Node (Rev. A)
Achieving a clean startup by using a DC/DC converter with a precise enable-pin threshold
Design considerations for a resistive feedback divider in a DC/DC converter
Methods of output-voltage adjustment for DC/DC converters
Choosing an Appropriate Pull-up/Pull-down Resistor for Open Drain Outputs
Using the TPS6215x in an Inverting Buck-Boost Topology.. (Rev. D)
How to Measure the Control Loop of DCS-Control Devices (Rev. A)
Testing tips for applying external power to supply outputs without an input voltage
Understanding 100% mode in low-power DC/DC converters
Understanding frequency variation in the DCS-Control(TM) topology