Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CD74HCT109MT | 74HCT109 Series |
|---|---|---|
| Clock Frequency | 54 MHz | 54 MHz |
| Current - Output High, Low | 4 mA, 4 mA | 4 mA |
| Current - Quiescent (Iq) | 4 çA | 4 çA |
| Function | Reset, Set(Preset) | Reset, Set(Preset) |
| Input Capacitance | 10 pF | 10 pF |
| Max Propagation Delay @ V, Max CL | 40 ns | 40 ns |
| Mounting Type | Surface Mount | Surface Mount, Through Hole |
| Number of Bits per Element | 1 | 1 |
| Number of Elements [custom] | 2 | 2 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 C | -55 C |
| Output Type | Complementary | Complementary |
| Package / Case | 16-SOIC | 16-SOIC, 16-DIP |
| Package / Case | 3.9 mm Width, 0.154 in | 0.154 - 7.62 mm Width |
| Supplier Device Package | 16-SOIC | 16-SOIC, 16-PDIP |
| Trigger Type | Positive Edge | Positive Edge |
| Type | JK Type | JK Type |
| Voltage - Supply [Max] | 5.5 V | 5.5 V |
| Voltage - Supply [Min] | 4.5 V | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
74HCT109 Series
High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
| Part | Max Propagation Delay @ V, Max CL | Input Capacitance | Supplier Device Package | Function | Number of Elements [custom] | Clock Frequency | Current - Quiescent (Iq) | Package / Case | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Mounting Type | Number of Bits per Element | Voltage - Supply [Max] | Voltage - Supply [Min] | Trigger Type | Output Type | Type | Current - Output High, Low |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HCT109M96The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.
The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. | 40 ns | 10 pF | 16-SOIC | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-SOIC | 0.154 in, 3.9 mm Width | -55 C | 125 °C | Surface Mount | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Texas Instruments CD74HCT109MThe ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.
The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. | 40 ns | 10 pF | 16-SOIC | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-SOIC | 0.154 in, 3.9 mm Width | -55 C | 125 °C | Surface Mount | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Texas Instruments CD74HCT109EThe ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.
The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition. | 40 ns | 10 pF | 16-PDIP | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-DIP | 0.3 in, 7.62 mm | -55 C | 125 °C | Through Hole | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Texas Instruments CD74HCT109MTFlip Flop 2 Element JK Type 1 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width) | 40 ns | 10 pF | 16-SOIC | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-SOIC | 0.154 in, 3.9 mm Width | -55 C | 125 °C | Surface Mount | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Description
General part information
74HCT109 Series
The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.
The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).