74HCT109 Series
High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
| Part | Max Propagation Delay @ V, Max CL | Input Capacitance | Supplier Device Package | Function | Number of Elements [custom] | Clock Frequency | Current - Quiescent (Iq) | Package / Case | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Mounting Type | Number of Bits per Element | Voltage - Supply [Max] | Voltage - Supply [Min] | Trigger Type | Output Type | Type | Current - Output High, Low |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HCT109M96 | 40 ns | 10 pF | 16-SOIC | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-SOIC | 0.154 in, 3.9 mm Width | -55 C | 125 °C | Surface Mount | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Texas Instruments CD74HCT109M | 40 ns | 10 pF | 16-SOIC | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-SOIC | 0.154 in, 3.9 mm Width | -55 C | 125 °C | Surface Mount | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Texas Instruments CD74HCT109E | 40 ns | 10 pF | 16-PDIP | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-DIP | 0.3 in, 7.62 mm | -55 C | 125 °C | Through Hole | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Texas Instruments CD74HCT109MT | 40 ns | 10 pF | 16-SOIC | Reset, Set(Preset) | 2 | 54 MHz | 4 çA | 16-SOIC | 0.154 in, 3.9 mm Width | -55 C | 125 °C | Surface Mount | 1 | 5.5 V | 4.5 V | Positive Edge | Complementary | JK Type | 4 mA, 4 mA |
Key Features
• Asynchronous Set and ResetSchmitt Trigger Clock InputsTypical fMAX= 54MHz at VCC= 5V, CL= 15pF, A = 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHAsynchronous Set and ResetSchmitt Trigger Clock InputsTypical fMAX= 54MHz at VCC= 5V, CL= 15pF, A = 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOH
Description
AI
The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.
The ’HC109 and ’HCT109 are dual J-K\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
The flip-flop is set and reset by active-low S\ and R\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.