The TPS753xxQ and TPS751xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled whenENis connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal toEN(enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ= +25°C. For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output for use with a power-on reset or a low-battery indicator. TheRESET(SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage,RESETgoes to a high-impedance state after a 100-ms delay.RESETgoes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage. The TPS751xxQ and TPS753xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available in a 20-pin TSSOP (PWP) package. The TPS753xxQ and TPS751xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled whenENis connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal toEN(enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ= +25°C. For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output for use with a power-on reset or a low-battery indicator. TheRESET(SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage,RESETgoes to a high-impedance state after a 100-ms delay.RESETgoes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage. The TPS751xxQ and TPS753xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available in a 20-pin TSSOP (PWP) package.

Linear Voltage Regulator IC Positive Adjustable 1 Output 1.5A 20-HTSSOP

The TPS753xxQ and TPS751xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled whenENis connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal toEN(enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ= +25°C. For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output for use with a power-on reset or a low-battery indicator. TheRESET(SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage,RESETgoes to a high-impedance state after a 100-ms delay.RESETgoes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage. The TPS751xxQ and TPS753xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available in a 20-pin TSSOP (PWP) package. The TPS753xxQ and TPS751xxQ devices are low-dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. These devices are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, because the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled whenENis connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal toEN(enable) shuts down the regulator, reducing the quiescent current to less than 1 µA at TJ= +25°C. For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output for use with a power-on reset or a low-battery indicator. TheRESET(SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage,RESETgoes to a high-impedance state after a 100-ms delay.RESETgoes to a logic-low state when the regulated output voltage is pulled below 95% (that is, during an overload condition) of its regulated voltage. The TPS751xxQ and TPS753xxQ are offered in 1.5 V, 1.8 V, 2.5 V and 3.3 V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available in a 20-pin TSSOP (PWP) package.

The TPS753xxQ and TPS751xxQ are low dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. TPS751xxQ and TPS753xxQ are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when EN\ is connected to a low level voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN\ (enable) shuts down the regulator, reducing the quiescent current to less than 1µA at TJ= 25°C. For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output, which can be used to implement a power-on reset or a low-battery indicator. The RESET\ (SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET\ goes to a high-impedance state after a 100-ms delay. RESET\ goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage. The TPS751xxQ or TPS753xxQ is offered in 1.5-V, 1.8-V, 2.5-V and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available in 20-pin TSSOP (PWP) packages. The TPS753xxQ and TPS751xxQ are low dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 µA at full load and drops down to 1 µA when the device is disabled. TPS751xxQ and TPS753xxQ are designed to have fast transient response for larger load current changes. Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 µA over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems. The device is enabled when EN\ is connected to a low level voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN\ (enable) shuts down the regulator, reducing the quiescent current to less than 1µA at TJ= 25°C. For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output, which can be used to implement a power-on reset or a low-battery indicator. The RESET\ (SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET\ goes to a high-impedance state after a 100-ms delay. RESET\ goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage. The TPS751xxQ or TPS753xxQ is offered in 1.5-V, 1.8-V, 2.5-V and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available in 20-pin TSSOP (PWP) packages.