CD54HC190F3A
ActiveHIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BCD DECADE UP/DOWN COUNTER
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CD54HC190F3A
ActiveHIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BCD DECADE UP/DOWN COUNTER
Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC190F3A |
|---|---|
| Count Rate | 35 MHz |
| Direction | Down, Up |
| Logic Type | BCD Counter, Decade |
| Mounting Type | Through Hole |
| Number of Bits per Element | 4 |
| Number of Elements [custom] | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 C |
| Package / Case | 16-CDIP (0.300", 7.62mm) |
| Reset | Asynchronous |
| Supplier Device Package | 16-CDIP |
| Timing | Synchronous |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
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CD54HC190 Series
High Speed CMOS Logic Presettable Synchronous 4-Bit BCD Decade Up/Down Counter
| Part | Timing | Reset | Trigger Type | Voltage - Supply [Max] | Voltage - Supply [Min] | Number of Elements [custom] | Direction | Mounting Type | Count Rate | Number of Bits per Element | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package | Logic Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HC190F3AThe CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3). | Synchronous | Asynchronous | Positive Edge | 6 V | 2 V | 1 | Down, Up | Through Hole | 35 MHz | 4 | 16-CDIP (0.300", 7.62mm) | -55 C | 125 °C | 16-CDIP | BCD Counter, Decade |
Description
General part information
CD54HC190 Series
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
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