CD54HC190 Series
High Speed CMOS Logic Presettable Synchronous 4-Bit BCD Decade Up/Down Counter
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
High Speed CMOS Logic Presettable Synchronous 4-Bit BCD Decade Up/Down Counter
| Part | Timing | Reset | Trigger Type | Voltage - Supply [Max] | Voltage - Supply [Min] | Number of Elements [custom] | Direction | Mounting Type | Count Rate | Number of Bits per Element | Package / Case | Operating Temperature [Min] | Operating Temperature [Max] | Supplier Device Package | Logic Type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HC190F3A | Synchronous | Asynchronous | Positive Edge | 6 V | 2 V | 1 | Down, Up | Through Hole | 35 MHz | 4 | 16-CDIP (0.300", 7.62mm) | -55 C | 125 °C | 16-CDIP | BCD Counter, Decade |
Key Features
• 2-V to 6-V VCCOperation (’HC190,191)4.5-V to 5.5-V VCCOperation (’HCT191)Wide Operating Temperature Range of –55 to 125°CSynchronous Counting and Asynchronous LoadingTwo Outputs for n-Bit CascadingLook-Ahead Carry for High-Speed CountingBalanced Propagation Delay and Transition TimesStandard Outputs Drive Up To 15 LS-TTL LoadsSignificant Power Reduction Compared to LS-TTL Logic ICs2-V to 6-V VCCOperation (’HC190,191)4.5-V to 5.5-V VCCOperation (’HCT191)Wide Operating Temperature Range of –55 to 125°CSynchronous Counting and Asynchronous LoadingTwo Outputs for n-Bit CascadingLook-Ahead Carry for High-Speed CountingBalanced Propagation Delay and Transition TimesStandard Outputs Drive Up To 15 LS-TTL LoadsSignificant Power Reduction Compared to LS-TTL Logic ICs
Description
AI
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).
The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.
Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.
When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).
If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).