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CD4023BE - 14-pin (N) package image

CD4023BE

Active
Texas Instruments

THREE-CHANNEL 3-INPUT 3V-TO-18V NAND GATE

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Search across all available documentation for this part.

DocumentsLogic Guide (Rev. AB)CD4011B, CD4012B, CD4023B TYPES datasheet (Rev. D)+5
CD4023BE - 14-pin (N) package image

CD4023BE

Active
Texas Instruments

THREE-CHANNEL 3-INPUT 3V-TO-18V NAND GATE

Deep-Dive with AI

DocumentsLogic Guide (Rev. AB)CD4011B, CD4012B, CD4023B TYPES datasheet (Rev. D)+5

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationCD4023BECD4023B Series
Current - Output High, Low3.4 mA, 3.4 mA3.4 mA
Current - Quiescent (Max) [Max]1 çA1 çA
Input Logic Level - High [Max]11 V11 V
Input Logic Level - High [Min]3.5 V3.5 V
Input Logic Level - Low [Max]4 V4 V
Input Logic Level - Low [Min]1.5 V1.5 V
Logic TypeNAND GateNAND Gate
Max Propagation Delay @ V, Max CL90 ns90 ns
Mounting TypeThrough HoleSurface Mount, Through Hole
Number of Circuits33
Number of Inputs33
Operating Temperature [Max]125 °C125 °C
Operating Temperature [Min]-55 °C-55 °C
Package / Case14-DIP14-SOIC, 14-TSSOP, 14-DIP
Package / Case7.62 mm3.9 - 7.62 mm
Package / Case0.3 in0.154 - 0.3 in
Package / Case-0.173 in
Package / Case-4.4 mm
Package / Case-5.3 mm
Package / Case-0.209 in
Supplier Device Package-14-TSSOP, 14-SO
Voltage - Supply [Max]18 V18 V
Voltage - Supply [Min]3 V3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.84
10$ 0.75
25$ 0.71
100$ 0.58
250$ 0.55
500$ 0.48
1000$ 0.38
2500$ 0.35
5000$ 0.34
Texas InstrumentsTUBE 1$ 0.62
100$ 0.48
250$ 0.35
1000$ 0.25

CD4023B Series

Three-channel 3-input 3V-to-18V NAND gate

PartInput Logic Level - High [Min]Input Logic Level - High [Max]Logic TypePackage / CasePackage / CasePackage / CaseMax Propagation Delay @ V, Max CLNumber of InputsMounting TypeNumber of CircuitsVoltage - Supply [Max]Voltage - Supply [Min]Operating Temperature [Min]Operating Temperature [Max]Input Logic Level - Low [Min]Input Logic Level - Low [Max]Current - Output High, LowCurrent - Quiescent (Max) [Max]Package / Case [custom]Package / Case [custom]Supplier Device PackagePackage / Case [y]Package / Case [y]
Texas Instruments
CD4023BM96
3.5 V
11 V
NAND Gate
3.9 mm
0.154 in
14-SOIC
90 ns
3
Surface Mount
3
18 V
3 V
-55 °C
125 °C
1.5 V
4 V
3.4 mA, 3.4 mA
1 çA
Texas Instruments
CD4023BPW
3.5 V
11 V
NAND Gate
14-TSSOP
90 ns
3
Surface Mount
3
18 V
3 V
-55 °C
125 °C
1.5 V
4 V
3.4 mA, 3.4 mA
1 çA
0.173 in
4.4 mm
14-TSSOP
Texas Instruments
CD4023BMT
3.5 V
11 V
NAND Gate
3.9 mm
0.154 in
14-SOIC
90 ns
3
Surface Mount
3
18 V
3 V
-55 °C
125 °C
1.5 V
4 V
3.4 mA, 3.4 mA
1 çA
Texas Instruments
CD4023BM
3.5 V
11 V
NAND Gate
3.9 mm
0.154 in
14-SOIC
90 ns
3
Surface Mount
3
18 V
3 V
-55 °C
125 °C
1.5 V
4 V
3.4 mA, 3.4 mA
1 çA
Texas Instruments
CD4023BNSR
3.5 V
11 V
NAND Gate
14-SOIC
90 ns
3
Surface Mount
3
18 V
3 V
-55 °C
125 °C
1.5 V
4 V
3.4 mA, 3.4 mA
1 çA
14-SO
5.3 mm
0.209 in
Texas Instruments
CD4023BPWR
3.5 V
11 V
NAND Gate
14-TSSOP
90 ns
3
Surface Mount
3
18 V
3 V
-55 °C
125 °C
1.5 V
4 V
3.4 mA, 3.4 mA
1 çA
0.173 in
4.4 mm
14-TSSOP
Texas Instruments
CD4023BE
3.5 V
11 V
NAND Gate
7.62 mm
0.3 in
14-DIP
90 ns
3
Through Hole
3
18 V
3 V
-55 °C
125 °C
1.5 V
4 V
3.4 mA, 3.4 mA
1 çA

Description

General part information

CD4023B Series

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in 14-lead thin shrink small-outline packages (PW suffix).

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.