CD74HC107M96
ActiveTexas Instruments
HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET
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CD74HC107M96
ActiveTexas Instruments
HIGH SPEED CMOS LOGIC DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH RESET
Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CD74HC107M96 | 74HC107 Series |
|---|---|---|
| Clock Frequency | 60 MHz | 60 MHz |
| Current - Output High, Low | 5.2 mA, 5.2 mA | 5.2 mA |
| Current - Quiescent (Iq) | 4 çA | 4 çA |
| Function | Reset | Reset |
| Input Capacitance | 10 pF | 10 pF |
| Max Propagation Delay @ V, Max CL | 29 ns | 29 ns |
| Mounting Type | Surface Mount | Surface Mount, Through Hole |
| Number of Bits per Element | 1 | 1 |
| Number of Elements [custom] | 2 | 2 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 C | -55 C |
| Output Type | Complementary | Complementary |
| Package / Case | 3.9 mm | 3.9 - 7.62 mm |
| Package / Case | 0.154 in | 0.154 - 0.3 in |
| Package / Case | 14-SOIC | 14-SOIC, 14-DIP |
| Trigger Type | Negative Edge | Negative Edge |
| Type | JK Type | JK Type |
| Voltage - Supply [Max] | 6 V | 6 V |
| Voltage - Supply [Min] | 2 V | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
74HC107 Series
High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset
| Part | Current - Output High, Low | Type | Number of Elements [custom] | Clock Frequency | Trigger Type | Number of Bits per Element | Output Type | Current - Quiescent (Iq) | Operating Temperature [Min] | Operating Temperature [Max] | Input Capacitance | Mounting Type | Voltage - Supply [Min] | Voltage - Supply [Max] | Function | Max Propagation Delay @ V, Max CL | Package / Case | Package / Case | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HC107MTThe ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family.
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family. | 5.2 mA, 5.2 mA | JK Type | 2 | 60 MHz | Negative Edge | 1 | Complementary | 4 çA | -55 C | 125 °C | 10 pF | Surface Mount | 2 V | 6 V | Reset | 29 ns | 3.9 mm | 0.154 in | 14-SOIC |
Texas Instruments CD74HC107M96The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family.
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family. | 5.2 mA, 5.2 mA | JK Type | 2 | 60 MHz | Negative Edge | 1 | Complementary | 4 çA | -55 C | 125 °C | 10 pF | Surface Mount | 2 V | 6 V | Reset | 29 ns | 3.9 mm | 0.154 in | 14-SOIC |
Texas Instruments CD74HC107MG4Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width) | 5.2 mA, 5.2 mA | JK Type | 2 | 60 MHz | Negative Edge | 1 | Complementary | 4 çA | -55 C | 125 °C | 10 pF | Surface Mount | 2 V | 6 V | Reset | 29 ns | 3.9 mm | 0.154 in | 14-SOIC |
Texas Instruments CD74HC107EThe ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family.
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family. | 5.2 mA, 5.2 mA | JK Type | 2 | 60 MHz | Negative Edge | 1 | Complementary | 4 çA | -55 C | 125 °C | 10 pF | Through Hole | 2 V | 6 V | Reset | 29 ns | 7.62 mm | 0.3 in | 14-DIP |
Texas Instruments CD74HC107MThe ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family.
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
The HCT logic family is functionally as well as pin compatible with the standard LS family. | 5.2 mA, 5.2 mA | JK Type | 2 | 60 MHz | Negative Edge | 1 | Complementary | 4 çA | -55 C | 125 °C | 10 pF | Surface Mount | 2 V | 6 V | Reset | 29 ns | 3.9 mm | 0.154 in | 14-SOIC |
Texas Instruments CD74HC107MTE4Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-SOIC (0.154", 3.90mm Width) | 5.2 mA, 5.2 mA | JK Type | 2 | 60 MHz | Negative Edge | 1 | Complementary | 4 çA | -55 C | 125 °C | 10 pF | Surface Mount | 2 V | 6 V | Reset | 29 ns | 3.9 mm | 0.154 in | 14-SOIC |
Texas Instruments CD74HC107EG4Flip Flop 2 Element JK Type 1 Bit Negative Edge 14-DIP (0.300", 7.62mm) | 5.2 mA, 5.2 mA | JK Type | 2 | 60 MHz | Negative Edge | 1 | Complementary | 4 çA | -55 C | 125 °C | 10 pF | Through Hole | 2 V | 6 V | Reset | 29 ns | 7.62 mm | 0.3 in | 14-DIP |
Description
General part information
74HC107 Series
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.
These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.
This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.
Documents
Technical documentation and resources