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74HC107 Series

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/

Catalog

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Reset

PartCurrent - Output High, LowTypeNumber of Elements [custom]Clock FrequencyTrigger TypeNumber of Bits per ElementOutput TypeCurrent - Quiescent (Iq)Operating Temperature [Min]Operating Temperature [Max]Input CapacitanceMounting TypeVoltage - Supply [Min]Voltage - Supply [Max]FunctionMax Propagation Delay @ V, Max CLPackage / CasePackage / CasePackage / Case
Texas Instruments
CD74HC107MT
5.2 mA, 5.2 mA
JK Type
2
60 MHz
Negative Edge
1
Complementary
4 çA
-55 C
125 °C
10 pF
Surface Mount
2 V
6 V
Reset
29 ns
3.9 mm
0.154 in
14-SOIC
Texas Instruments
CD74HC107M96
5.2 mA, 5.2 mA
JK Type
2
60 MHz
Negative Edge
1
Complementary
4 çA
-55 C
125 °C
10 pF
Surface Mount
2 V
6 V
Reset
29 ns
3.9 mm
0.154 in
14-SOIC
Texas Instruments
CD74HC107MG4
5.2 mA, 5.2 mA
JK Type
2
60 MHz
Negative Edge
1
Complementary
4 çA
-55 C
125 °C
10 pF
Surface Mount
2 V
6 V
Reset
29 ns
3.9 mm
0.154 in
14-SOIC
Texas Instruments
CD74HC107E
5.2 mA, 5.2 mA
JK Type
2
60 MHz
Negative Edge
1
Complementary
4 çA
-55 C
125 °C
10 pF
Through Hole
2 V
6 V
Reset
29 ns
7.62 mm
0.3 in
14-DIP
Texas Instruments
CD74HC107M
5.2 mA, 5.2 mA
JK Type
2
60 MHz
Negative Edge
1
Complementary
4 çA
-55 C
125 °C
10 pF
Surface Mount
2 V
6 V
Reset
29 ns
3.9 mm
0.154 in
14-SOIC
Texas Instruments
CD74HC107MTE4
5.2 mA, 5.2 mA
JK Type
2
60 MHz
Negative Edge
1
Complementary
4 çA
-55 C
125 °C
10 pF
Surface Mount
2 V
6 V
Reset
29 ns
3.9 mm
0.154 in
14-SOIC
Texas Instruments
CD74HC107EG4
5.2 mA, 5.2 mA
JK Type
2
60 MHz
Negative Edge
1
Complementary
4 çA
-55 C
125 °C
10 pF
Through Hole
2 V
6 V
Reset
29 ns
7.62 mm
0.3 in
14-DIP

Key Features

• Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall TimesAsynchronous ResetComplementary OutputsBuffered InputsTypical fMAX= 60MHz at VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOHHysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall TimesAsynchronous ResetComplementary OutputsBuffered InputsTypical fMAX= 60MHz at VCC= 5V, CL= 15pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL LoadsBus Driver Outputs . . . . . . . . . . . . . 15 LSTTL LoadsWide Operating Temperature Range . . . -55°C to 125°CBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHC Types2V to 6V OperationHigh Noise Immunity: NIL= 30%, NIH= 30% of VCCat VCC= 5VHCT Types4.5V to 5.5V OperationDirect LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH= 2V (Min)CMOS Input Compatibility, Il1µA at VOL, VOH

Description

AI
The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family. The ’HC107 and ’HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads. These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input. This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits. The HCT logic family is functionally as well as pin compatible with the standard LS family.