CD54HC4060F3A
ActiveHIGH SPEED CMOS LOGIC 14-STAGE BINARY COUNTER WITH OSCILLATOR
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CD54HC4060F3A
ActiveHIGH SPEED CMOS LOGIC 14-STAGE BINARY COUNTER WITH OSCILLATOR
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC4060F3A |
|---|---|
| Count Rate | 35 MHz |
| Direction | Up |
| Logic Type | Binary Counter |
| Mounting Type | Through Hole |
| Number of Bits per Element | 14 |
| Number of Elements [custom] | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 C |
| Package / Case | 16-CDIP (0.300", 7.62mm) |
| Reset | Asynchronous |
| Supplier Device Package | 16-CDIP |
| Trigger Type | Negative Edge |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
CD54HC4060 Series
High Speed CMOS Logic 14-Stage Binary Counter with Oscillator
| Part | Count Rate | Logic Type | Operating Temperature [Min] | Operating Temperature [Max] | Number of Bits per Element | Reset | Voltage - Supply [Max] | Voltage - Supply [Min] | Direction | Mounting Type | Package / Case | Trigger Type | Supplier Device Package | Number of Elements [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HC4060F3AThe ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.
The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels. | 35 MHz | Binary Counter | -55 C | 125 °C | 14 | Asynchronous | 6 V | 2 V | Up | Through Hole | 16-CDIP (0.300", 7.62mm) | Negative Edge | 16-CDIP | 1 |
Description
General part information
CD54HC4060 Series
The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.
The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
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