CD74AC109M96
ActiveDUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
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CD74AC109M96
ActiveDUAL POSITIVE-EDGE-TRIGGERED J-K FLIP-FLOPS WITH SET AND RESET
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CD74AC109M96 | CD74AC109 Series |
|---|---|---|
| Clock Frequency | 100 MHz | 100 MHz |
| Current - Output High, Low [custom] | 24 mA | 24 mA |
| Current - Output High, Low [custom] | 24 mA | 24 mA |
| Current - Quiescent (Iq) | 4 çA | 4 çA |
| Function | Reset, Set(Preset) | Reset, Set(Preset) |
| Input Capacitance | 10 pF | 10 pF |
| Max Propagation Delay @ V, Max CL | 10.3 ns | 10.3 ns |
| Mounting Type | Surface Mount | Surface Mount, Through Hole |
| Number of Bits per Element | 1 | 1 |
| Number of Elements [custom] | 2 | 2 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 C | -55 C |
| Output Type | Complementary | Complementary |
| Package / Case | 16-SOIC | 16-SOIC, 16-DIP |
| Package / Case | 3.9 mm Width, 0.154 in | 0.154 - 7.62 mm Width |
| Supplier Device Package | 16-SOIC | 16-SOIC, 16-PDIP |
| Trigger Type | Positive Edge | Positive Edge |
| Type | JK Type | JK Type |
| Voltage - Supply [Max] | 5.5 V | 5.5 V |
| Voltage - Supply [Min] | 1.5 V | 1.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
CD74AC109 Series
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
| Part | Mounting Type | Number of Bits per Element | Input Capacitance | Number of Elements [custom] | Max Propagation Delay @ V, Max CL | Clock Frequency | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Type | Output Type | Current - Quiescent (Iq) | Voltage - Supply [Min] | Voltage - Supply [Max] | Trigger Type | Package / Case | Package / Case | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] | Function |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74AC109M96The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.
The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications. | Surface Mount | 1 | 10 pF | 2 | 10.3 ns | 100 MHz | 24 mA | 24 mA | JK Type | Complementary | 4 çA | 1.5 V | 5.5 V | Positive Edge | 16-SOIC | 0.154 in, 3.9 mm Width | 16-SOIC | -55 C | 125 °C | Reset, Set(Preset) |
Texas Instruments CD74AC109EThe CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.
The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications. | Through Hole | 1 | 10 pF | 2 | 10.3 ns | 100 MHz | 24 mA | 24 mA | JK Type | Complementary | 4 çA | 1.5 V | 5.5 V | Positive Edge | 16-DIP | 0.3 in, 7.62 mm | 16-PDIP | -55 C | 125 °C | Reset, Set(Preset) |
Description
General part information
CD74AC109 Series
The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.
The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.
Documents
Technical documentation and resources