CD74AC109 Series
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset
| Part | Mounting Type | Number of Bits per Element | Input Capacitance | Number of Elements [custom] | Max Propagation Delay @ V, Max CL | Clock Frequency | Current - Output High, Low [custom] | Current - Output High, Low [custom] | Type | Output Type | Current - Quiescent (Iq) | Voltage - Supply [Min] | Voltage - Supply [Max] | Trigger Type | Package / Case | Package / Case | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] | Function |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74AC109M96 | Surface Mount | 1 | 10 pF | 2 | 10.3 ns | 100 MHz | 24 mA | 24 mA | JK Type | Complementary | 4 çA | 1.5 V | 5.5 V | Positive Edge | 16-SOIC | 0.154 in, 3.9 mm Width | 16-SOIC | -55 C | 125 °C | Reset, Set(Preset) |
Texas Instruments CD74AC109E | Through Hole | 1 | 10 pF | 2 | 10.3 ns | 100 MHz | 24 mA | 24 mA | JK Type | Complementary | 4 çA | 1.5 V | 5.5 V | Positive Edge | 16-DIP | 0.3 in, 7.62 mm | 16-PDIP | -55 C | 125 °C | Reset, Set(Preset) |
Key Features
• AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltageSpeed of bipolar F, AS, and S, with significantly reduced power consumptionBalanced propagation delays±24mA output drive currentFanout to 15 F devicesSCR-latchup-resistant CMOS process and circuit designExceeds 2kV ESD protection per MIL-STD-883, method 3015AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltageSpeed of bipolar F, AS, and S, with significantly reduced power consumptionBalanced propagation delays±24mA output drive currentFanout to 15 F devicesSCR-latchup-resistant CMOS process and circuit designExceeds 2kV ESD protection per MIL-STD-883, method 3015
Description
AI
The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.
The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications.