CDCF2509PWR
Active3.3-V PLL CLOCK DRIVER WITH SUPPORT FOR PC133 SDRAM REGISTERED DIMM SPECIFICATION REV. 0.9
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CDCF2509PWR
Active3.3-V PLL CLOCK DRIVER WITH SUPPORT FOR PC133 SDRAM REGISTERED DIMM SPECIFICATION REV. 0.9
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CDCF2509PWR | CDCF2509 Series |
|---|---|---|
| Differential - Input:Output [custom] | False | False |
| Differential - Input:Output [custom] | False | False |
| Frequency - Max [Max] | 140 MHz | 140 MHz |
| Input | Clock | Clock |
| Main Purpose | Memory, DRAM DIMM | Memory, DRAM DIMM |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | 0 °C | 0 °C |
| Output | Clock | Clock |
| Package / Case | 24-TSSOP | 24-TSSOP |
| Package / Case [y] | 4.4 mm | 4.4 mm |
| Package / Case [y] | 0.173 " | 0.173 " |
| PLL | True | True |
| Ratio - Input:Output [custom] | 1 | 1 |
| Ratio - Input:Output [custom] | 9 | 9 |
| Supplier Device Package | 24-TSSOP | 24-TSSOP |
| Voltage - Supply [Max] | 3.6 V | 3.6 V |
| Voltage - Supply [Min] | 3 V | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 8.64 | |
| Texas Instruments | LARGE T&R | 1 | $ 12.76 | |
| 100 | $ 11.15 | |||
| 250 | $ 8.59 | |||
| 1000 | $ 7.69 | |||
CDCF2509 Series
3.3-V PLL clock driver with support for PC133 SDRAM registered DIMM specification rev. 0.9
| Part | Number of Circuits | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Output | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] | Main Purpose | Frequency - Max [Max] | Input | PLL | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Mounting Type | Package / Case [y] | Package / Case [y] | Package / Case | Voltage - Supply [Max] | Voltage - Supply [Min] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCF2509PWR | 1 | 1 | 9 | Clock | 24-TSSOP | 0 °C | 85 °C | DRAM DIMM, Memory | 140 MHz | Clock | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 3.6 V | 3 V | |||
Texas Instruments CDCF2509PW | 1 | 1 | 9 | Clock | 24-TSSOP | 0 °C | 85 °C | DRAM DIMM, Memory | 140 MHz | Clock | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 3.6 V | 3 V | |||
Texas Instruments CDCF2509PWG4 | 1 | 1 | 9 | Clock | 24-TSSOP | 0 °C | 85 °C | DRAM DIMM, Memory | 140 MHz | Clock | Surface Mount | 4.4 mm | 0.173 " | 24-TSSOP | 3.6 V | 3 V |
Description
General part information
CDCF2509 Series
The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Documents
Technical documentation and resources