CDCF2509 Series

3.3-V PLL clock driver with support for PC133 SDRAM registered DIMM specification rev. 0.9

Link to Manufacturer Page: https://www.ti.com/

Catalog

3.3-V PLL clock driver with support for PC133 SDRAM registered DIMM specification rev. 0.9

Part	Number of Circuits	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Output	Supplier Device Package	Operating Temperature [Max]	Main Purpose	Frequency - Max [Max]	Input	Mounting Type	Package / Case [y]	Package / Case [y]	Package / Case	Voltage - Supply [Max]	Voltage - Supply [Min]
Texas Instruments CDCF2509PWR	1	1	9	Clock	24-TSSOP	85 °C	DRAM DIMM, Memory	140 MHz	Clock	Surface Mount	4.4 mm	0.173 "	24-TSSOP	3.6 V	3 V
Texas Instruments CDCF2509PW	1	1	9	Clock	24-TSSOP	85 °C	DRAM DIMM, Memory	140 MHz	Clock	Surface Mount	4.4 mm	0.173 "	24-TSSOP	3.6 V	3 V
Texas Instruments CDCF2509PWG4	1	1	9	Clock	24-TSSOP	85 °C	DRAM DIMM, Memory	140 MHz	Clock	Surface Mount	4.4 mm	0.173 "	24-TSSOP	3.6 V	3 V

Key Features

• UseCDCVF2509Aas a Replacement for this DeviceDesigned to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9Spread Spectrum Clock CompatibleOperating Frequency 25 MHz to 140 MHzStatic Phase Error Distribution at 66 MHz to 133 MHz is ±125 psJitter (cyc-cyc) at 66 MHz to 133 MHz Is |70| psAvailable in Plastic 24-Pin TSSOPPhase-Lock Loop Clock Distribution for Synchronous DRAM ApplicationsDistributes One Clock Input to One Bank of Five and One Bank of Four OutputsSeparate Output Enable for Each Output BankExternal Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock InputOn-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 VUseCDCVF2509Aas a Replacement for this DeviceDesigned to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9Spread Spectrum Clock CompatibleOperating Frequency 25 MHz to 140 MHzStatic Phase Error Distribution at 66 MHz to 133 MHz is ±125 psJitter (cyc-cyc) at 66 MHz to 133 MHz Is |70| psAvailable in Plastic 24-Pin TSSOPPhase-Lock Loop Clock Distribution for Synchronous DRAM ApplicationsDistributes One Clock Input to One Bank of Five and One Bank of Four OutputsSeparate Output Enable for Each Output BankExternal Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock InputOn-Chip Series Damping ResistorsNo External RC Network RequiredOperates at 3.3 V

Description

The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground. The CDCF2509 is characterized for operation from 0°C to 85°C. For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039). The CDCF2509 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCF2509 operates at 3.3 V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CDCF2509 does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CDCF2509 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCCto ground. The CDCF2509 is characterized for operation from 0°C to 85°C. For application information refer to application reportsHigh Speed Distribution Design Techniques for CDC509/516/2509/2510/2516(literature number SLMA003) andUsing CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC)(literature number SCAA039).