The ADC32RF5x is a single core 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converters (ADC) that supports RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -161 dBFS/Hz. Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The ADC32RF54 and ADC32RF55 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. The power efficient ADC architecture consumes 2.1 W/ch at 3 Gsps and provides power scaling with lower sampling rates. The ADC32RF5x is a single core 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converters (ADC) that supports RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -161 dBFS/Hz. Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The ADC32RF54 and ADC32RF55 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. The power efficient ADC architecture consumes 2.1 W/ch at 3 Gsps and provides power scaling with lower sampling rates.

The ADC32RF5x is a single core 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converters (ADC) that supports RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -161 dBFS/Hz. Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The ADC32RF54 and ADC32RF55 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. The power efficient ADC architecture consumes 2.1 W/ch at 3 Gsps and provides power scaling with lower sampling rates. The ADC32RF5x is a single core 14-bit, 2.6 GSPS to 3 GSPS, dual channel analog to digital converters (ADC) that supports RF sampling with input frequencies up to 3 GHz. The design maximizes signal-to-noise ratio (SNR) and delivers a noise spectral density of -155 dBFS/Hz. Using additional internal ADCs along with on-chip signal averaging, the noise density improves to -161 dBFS/Hz. Each ADC channel can be connected to a quad-band digital down-converter (DDC) using a 48-bit NCO which supports phase coherent frequency hopping. Using the GPIO pins for NCO frequency control, frequency hopping can be achieved in less than 1 µs. The ADC32RF54 and ADC32RF55 supports the JESD204B serial data interface with subclass 1 deterministic latency using data rates up to 13 Gbps. The power efficient ADC architecture consumes 2.1 W/ch at 3 Gsps and provides power scaling with lower sampling rates.