ADC3224 Series

Dual-Channel, 12-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

Catalog(3 parts)

Part	Number of A/D Converters▲▼	Sampling Rate (Per Second)▲▼	Number of Bits▲▼	Supplied Contents	Input Range▲▼	Utilized IC / Part	Power (Typ) @ Conditions▲▼	Data Interface	Reference Type	Supplier Device Package	Voltage - Supply, Analog▲▼	Voltage - Supply, Analog▲▼	Package / Case	Operating Temperature▲▼	Operating Temperature▲▼	Features	Input Type	Architecture	Voltage - Supply, Digital▲▼	Voltage - Supply, Digital▲▼	Mounting Type	Number of Inputs▲▼	Ratio - S/H:ADC	Configuration
Texas Instruments ADC3224EVM ADC3224 - 12 Bit 125M Samples per Second Analog to Digital Converter (ADC) Evaluation Board	2 ul	125 m	12 ul	Board(s)	2 ul	ADC3224	0.2329999953508377 W	LVDS - Serial
Texas Instruments ADC3224IRGZR 12 Bit Analog to Digital Converter 2 Input 2 Pipelined 48-VQFN (7x7)	2 ul	125 m	12 ul					LVDS - Serial	External, Internal	48-VQFN (7x7)	1.7000000476837158 V	1.899999976158142 V	48-VFQFN Exposed Pad	-40 °C	85 °C	Simultaneous Sampling	Differential	Pipelined	1.7000000476837158 V	1.899999976158142 V	Surface Mount	2 ul	0:1	ADC
Texas Instruments ADC3224IRGZT 12 Bit Analog to Digital Converter 2 Input 2 Pipelined 48-VQFN (7x7)	2 ul	125 m	12 ul					LVDS - Serial	External, Internal	48-VQFN (7x7)	1.7000000476837158 V	1.899999976158142 V	48-VFQFN Exposed Pad	-40 °C	85 °C	Simultaneous Sampling	Differential	Pipelined	1.7000000476837158 V	1.899999976158142 V	Surface Mount	2 ul		ADC

Key Features

• Dual channel12-Bit resolutionSingle supply: 1.8 VSerial LVDS interface (SLVDS)Flexible input clock buffer with divide-by-1, -2, -4SNR = 70.2 dBFS, SFDR = 87 dBc at fIN= 70 MHzUltra-low power consumption:116 mW/Ch at 125 MSPSChannel isolation: 105 dBInternal dither and chopperSupport for multi-chip synchronizationPin-to-pin compatible with 14-Bit versionPackage: VQFN-48 (7 mm × 7 mm)Dual channel12-Bit resolutionSingle supply: 1.8 VSerial LVDS interface (SLVDS)Flexible input clock buffer with divide-by-1, -2, -4SNR = 70.2 dBFS, SFDR = 87 dBc at fIN= 70 MHzUltra-low power consumption:116 mW/Ch at 125 MSPSChannel isolation: 105 dBInternal dither and chopperSupport for multi-chip synchronizationPin-to-pin compatible with 14-Bit versionPackage: VQFN-48 (7 mm × 7 mm)

Description

The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs. The ADC322x are a high-linearity, ultra-low power, dual-channel, 12-bit, 25-MSPS to 125-MSPS, analog-to-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. An input clock divider allows more flexibility for system clock architecture design and the SYSREF input enables complete system synchronization. The ADC322x family supports serial low-voltage differential signaling (LVDS) in order to reduce the number of interface lines, thus allowing for high system integration density. The serial LVDS interface is two-wire, where each ADC data are serialized and output over two LVDS pairs. Optionally, a one-wire serial LVDS interface is available. An internal phase-locked loop (PLL) multiplies the incoming ADC sampling clock to derive the bit clock that is used to serialize the 12-bit output data from each channel. In addition to the serial data streams, the frame and bit clocks are also transmitted as LVDS outputs.