CDC351 Series

1-line to 10-line 3.3-V clock driver with tri-state outputs

Catalog

1-line to 10-line 3.3-V clock driver with tri-state outputs

Part	Mounting Type	Frequency - Max	Type	Differential Output	Differential Input	Output	Package Length	Package Name	Package Width	Output Ratio	Input Ratio	Number of Circuits	Operating Temperature (Max)	Operating Temperature (Min)	Input	Voltage - Supply (Maximum)	Voltage - Supply (Minimum)
Texas Instruments CDC351DBR	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.209 in	24-SSOP	5.3 mm	10	1	1	70 °C	0 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351IDWRG4	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.295 in	24-SOIC	7.5 mm	10	1	1	85 °C	-40 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351IDWG4	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.295 in	24-SOIC	7.5 mm	10	1	1	85 °C	-40 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351DBRG4	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.209 in	24-SSOP	5.3 mm	10	1	1	70 °C	0 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351IDBG4	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.209 in	24-SSOP	5.3 mm	10	1	1	85 °C	-40 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351DWG4	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.295 in	24-SOIC	7.5 mm	10	1	1	70 °C	0 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351IDW	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.295 in	24-SOIC	7.5 mm	10	1	1	85 °C	-40 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351IDB	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.209 in	24-SSOP	5.3 mm	10	1	1	85 °C	-40 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351DWR	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.295 in	24-SOIC	7.5 mm	10	1	1	70 °C	0 °C	LVTTL	3.6 V	3 V
Texas Instruments CDC351IDWR	Surface Mount	100 MHz	Fanout Buffer (Distribution)	No	No	LVTTL TRI-State	0.295 in	24-SOIC	7.5 mm	10	1	1	85 °C	-40 °C	LVTTL	3.6 V	3 V

Catalog

1-line to 10-line 3.3-V clock driver with tri-state outputs

Description

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC. The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND. The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum skew for clock distribution. The output-enable (OE)\ input disables the outputs to a high-impedance state. The CDC351 operates at nominal 3.3-V VCC. The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer use and should be connected to GND.